NLV74HC175ADTR2G

更新时间： 2024-09-15 12:22:51

品牌	Logo	应用领域
安森美 - ONSEMI		触发器时钟
页数	文件大小	规格书
11页	157K
描述
Quad D Flip-Flop with Common Clock and Reset

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NLV74HC175ADTR2G 数据手册

MC74HC175A

Quad D Flip-Flop with

Common Clock and Reset

High−Performance Silicon−Gate CMOS

The MC74HC175A is identical in pinout to the LS175. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device consists of four D flip−flops with common Reset and

Clock inputs, and separate D inputs. Reset (active−low) is

asynchronous and occurs when a low level is applied to the Reset

input. Information at a D input is transferred to the corresponding Q

output on the next positive going edge of the Clock input.

http://onsemi.com

MARKING

DIAGRAMS

PDIP−16

N SUFFIX

CASE 648

MC74HC175AN

AWLYYWWG

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1 mA

SOIC−16

D SUFFIX

CASE 751B

HC175AG

AWLYWW

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7 A

TSSOP−16

DT SUFFIX

CASE 948F

175A

ALYWG

• Chip Complexity 166 FETs or 41.5 Equivalent Gates

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

L, WL

Y, YY

= Assembly Location

= Wafer Lot

= Year

Compliant

W, WW = Work Week

G or G

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Publication Order Number:

July, 2012 − Rev. 5

MC74HC175A/D

12 3 4 5 6 7...11

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