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NLV74HC273ADWR2G PDF预览

NLV74HC273ADWR2G

更新时间： 2024-09-17 01:23:43
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 96K
描述
Octal D Flip-Flop with Common Clock and Reset

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NLV74HC273ADWR2G 数据手册

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MC74HC273A  
Octal D Flip-Flop with  
Common Clock and Reset  
High−Performance Silicon−Gate CMOS  
The MC74HC273A is identical in pinout to the LS273. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
www.onsemi.com  
This device consists of eight D flip−flops with common Clock and  
Reset inputs. Each flip−flop is loaded with a low−to−high transition of  
the Clock input. Reset is asynchronous and active low.  
SOIC−20  
DW SUFFIX  
CASE 751D  
TSSOP−20  
DT SUFFIX  
CASE 948E  
Features  
• Output Drive Capability: 10 LSTTL Loads  
• Outputs Directly Interface to CMOS, NMOS and TTL  
• Operating Voltage Range: 2.0 to 6.0 V  
• Low Input Current: 1.0 mA  
PIN ASSIGNMENT  
RESET  
1
20  
V
CC  
Q0  
D0  
2
19 Q7  
18 D7  
17 D6  
16 Q6  
15 Q5  
14 D5  
13 D4  
12 Q4  
11 CLOCK  
3
• High Noise Immunity Characteristic of CMOS Devices  
D1  
4
• In Compliance with the Requirements Defined by JEDEC Standard  
Q1  
5
No. 7 A  
Q2  
6
• Chip Complexity: 264 FETs or 66 Equivalent Gates  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
D2  
7
D3  
8
Q3  
9
GND  
10  
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant  
MARKING DIAGRAMS  
LOGIC DIAGRAM  
20  
20  
2
3
Q0  
D0  
HC  
5
6
HC273A  
AWLYYWWG  
4
273A  
ALYWG  
G
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
7
8
9
DATA  
INPUTS  
1
NONINVERTING  
OUTPUTS  
1
13  
14  
17  
18  
12  
15  
16  
19  
SOIC−20  
TSSOP−20  
A
= Assembly Location  
= Wafer Lot  
= Year  
WL, L  
YY, Y  
WW, W = Work Week  
G or G  
= Pb−Free Package  
11  
CLOCK  
(Note: Microdot may be in either location)  
PIN 20 = V  
CC  
PIN 10 = GND  
FUNCTION TABLE  
1
RESET  
Inputs  
Output  
Q
Reset Clock  
D
Design Criteria  
Value  
66  
Units  
ea  
L
X
L
X
H
L
X
X
L
H
L
H
H
H
H
Internal Gate Count*  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
1.5  
ns  
No Change  
No Change  
5.0  
mW  
pJ  
Speed Power Product  
.0075  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
*Equivalent to a two−input NAND gate.  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
October, 2015 − Rev. 17  
MC74HC273A/D  
12345678

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