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NLV74HC374ADWG PDF预览

NLV74HC374ADWG

更新时间: 2024-09-17 01:13:11
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安森美 - ONSEMI /
页数 文件大小 规格书
7页 122K
描述
Octal 3-State Non-Inverting D Flip-Flop

NLV74HC374ADWG 数据手册

 浏览型号NLV74HC374ADWG的Datasheet PDF文件第2页浏览型号NLV74HC374ADWG的Datasheet PDF文件第3页浏览型号NLV74HC374ADWG的Datasheet PDF文件第4页浏览型号NLV74HC374ADWG的Datasheet PDF文件第5页浏览型号NLV74HC374ADWG的Datasheet PDF文件第6页浏览型号NLV74HC374ADWG的Datasheet PDF文件第7页 
MC74HC374A  
Octal 3-State Non-Inverting  
D Flip-Flop  
High−Performance Silicon−Gate CMOS  
The MC74HC374A is identical in pinout to the LS374. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
http://onsemi.com  
Data meeting the setup time is clocked to the outputs with the rising  
edge of the clock. The Output Enable input does not affect the states of  
the flip−flops, but when Output Enable is high, the outputs are forced  
to the high−impedance state; thus, data may be stored even when the  
outputs are not enabled.  
SOIC−20  
DW SUFFIX  
CASE 751D  
TSSOP−20  
DT SUFFIX  
CASE 948E  
The HC374A is identical in function to the HC574A which has the  
input pins on the opposite side of the package from the output. This  
device is similar in function to the HC534A which has inverting  
outputs.  
PIN ASSIGNMENT  
OUTPUT  
ENABLE  
1
V
Q7  
D7  
D6  
Q6  
Q5  
D5  
D4  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CC  
Q0  
D0  
D1  
Q1  
Q2  
D2  
D3  
Q3  
GND  
2
3
4
5
6
Features  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 mA  
7
8
9
10  
Q4  
CLOCK  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
MARKING DIAGRAMS  
No. 7 A  
20  
20  
1
Chip Complexity: 266 FETs or 66.5 Equivalent Gates  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
HC  
74HC374A  
AWLYYWWG  
374A  
ALYWG  
G
1
These Devices are Pb−Free and are RoHS Compliant  
SOIC−20  
TSSOP−20  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
LOGIC DIAGRAM  
2
3
Q0  
D0  
WW, W = Work Week  
5
6
4
G or G  
= Pb−Free Package  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
(Note: Microdot may be in either location)  
7
8
9
FUNCTION TABLE  
DATA  
NONINVERTING  
OUTPUTS  
13  
14  
17  
18  
INPUTS  
12  
15  
16  
19  
Inputs  
Output  
Output  
Enable Clock  
D
Q
L
L
L
H
L
X
X
H
L
No Change  
Z
L,H,  
X
11  
CLOCK  
H
X = don’t care  
Z = high impedance  
PIN 20 = V  
CC  
PIN 10 = GND  
1
OUTPUT ENABLE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
Publication Order Number:  
August, 2014 − Rev. 14  
MC74HC374A/D  

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