MC74HC245A
Octal 3-State Noninverting
Bus Transceiver
High−Performance Silicon−Gate CMOS
The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
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The HC245A is a 3−state noninverting transceiver that is used for
2−way asynchronous communication between data buses. The device
has an active−low Output Enable pin, which is used to place the I/O
ports into high−impedance states. The Direction control determines
whether data flows from A to B or from B to A.
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
Features
PIN ASSIGNMENT
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Chip Complexity: 308 FETs or 77 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
DIRECTION
20
V
CC
1
2
3
4
5
6
7
8
9
OUTPUT
ENABLE
A1
A2
A3
19
18
17
B1
B2
A4
A5
16
15
14
13
12
11
B3
B4
B5
B6
B7
B8
A6
A7
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
A8
LOGIC DIAGRAM
GND
10
2
18
17
16
15
14
13
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
3
4
5
6
7
MARKING DIAGRAMS
B3
B4
20
20
A
DATA
PORT
B
DATA
PORT
HC
B5
B6
B7
B8
HC245A
AWLYYWWG
245A
ALYWG
G
8
9
12
11
1
1
SOIC−20
TSSOP−20
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
DIRECTION
19
OUTPUT
ENABLE
PIN 10 = GND
PIN 20 = V
WW, W = Work Week
CC
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
November, 2014 − Rev. 16
MC74HC245A/D