Datasheet > NLV74HC273ADTR2G

NLV74HC273ADTR2G

更新时间： 2024-11-07 01:23:43

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	96K
描述
Octal D Flip-Flop with Common Clock and Reset

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NLV74HC273ADTR2G 数据手册

MC74HC273A

Octal D Flip-Flop with

Common Clock and Reset

High−Performance Silicon−Gate CMOS

The MC74HC273A is identical in pinout to the LS273. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

www.onsemi.com

This device consists of eight D flip−flops with common Clock and

Reset inputs. Each flip−flop is loaded with a low−to−high transition of

the Clock input. Reset is asynchronous and active low.

SOIC−20

DW SUFFIX

CASE 751D

TSSOP−20

DT SUFFIX

CASE 948E

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

PIN ASSIGNMENT

RESET

19 Q7

18 D7

17 D6

16 Q6

15 Q5

14 D5

13 D4

12 Q4

11 CLOCK

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7 A

• Chip Complexity: 264 FETs or 66 Equivalent Gates

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

GND

• These Devices are Pb−Free, Halogen Free and are RoHS Compliant

MARKING DIAGRAMS

LOGIC DIAGRAM

HC273A

AWLYYWWG

273A

ALYWG

DATA

INPUTS

NONINVERTING

OUTPUTS

SOIC−20

TSSOP−20

= Assembly Location

= Wafer Lot

= Year

WL, L

YY, Y

WW, W = Work Week

G or G

= Pb−Free Package

CLOCK

(Note: Microdot may be in either location)

PIN 20 = V

PIN 10 = GND

FUNCTION TABLE

RESET

Inputs

Output

Reset Clock

Design Criteria

Value

Units

Internal Gate Count*

Internal Gate Propagation Delay

Internal Gate Power Dissipation

1.5

No Change

5.0

Speed Power Product

.0075

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

*Equivalent to a two−input NAND gate.

Publication Order Number:

October, 2015 − Rev. 17

MC74HC273A/D

12 3 4 5 6 7 8

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