Datasheet > NLV74HC259ADTR2G

NLV74HC259ADTR2G

更新时间： 2024-11-26 11:11:39

品牌	Logo	应用领域
安森美 - ONSEMI		解码器
页数	文件大小	规格书
9页	246K
描述
8 位可寻址锁存 1/8 解码器

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NLV74HC259ADTR2G 数据手册

MC74HC259A

8-Bit Addressable Latch

1-of-8 Decoder

High−Performance Silicon−Gate CMOS

The MC74HC259A is identical in pinout to the LS259. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

http://onsemi.com

MARKING

The HC259A has four modes of operation as shown in the mode

selection table. In the addressable latch mode, the data on Data In is

written into the addressed latch. The addressed latch follows the data

input with all non−addressed latches remaining in their previous

states. In the memory mode, all latches remain in their previous state

and are unaffected by the Data or Address inputs. In the one−of−eight

decoding or demultiplexing mode, the addressed output follows the

state of Data In with all other outputs in the LOW state. In the Reset

mode all outputs are LOW and unaffected by the address and data

inputs. When operating the HC259A as an addressable latch, changing

more than one bit of the address could impose a transient wrong

address. Therefore, this should only be done while in the memory

mode.

DIAGRAMS

SOIC−16

D SUFFIX

CASE 751B

HC259AG

AWLYWW

TSSOP−16

DT SUFFIX

CASE 948F

259A

ALYWG

= Assembly Location

= Wafer Lot

WL, L

YY, Y

= Year

Features

WW, W = Work Week

G or G

= Pb−Free Package

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 mA

(Note: Microdot may be in either location)

PIN ASSIGNMENT

• High Noise Immunity Characteristic of CMOS Devices

15 RESET

14 ENABLE

13 DATA IN

12 Q7

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free and are RoHS Compliant

11 Q6

10 Q5

GND

MODE SELECTION TABLE

Enable Reset

Mode

Addressable Latch

Memory

8−Line Demultiplexer

Reset

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

Publication Order Number:

June, 2012 − Rev. 3

MC74HC259A/D

12 3 4 5 6 7...9

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