Datasheet > NLV74HC132ADR2G

NLV74HC132ADR2G

更新时间： 2024-09-14 01:09:31

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
9页	145K
描述
Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

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NLV74HC132ADR2G 数据手册

MC74HC132A

Quad 2-Input NAND Gate

with Schmitt-Trigger Inputs

High−Performance Silicon−Gate CMOS

The MC74HC132A is identical in pinout to the LS132. The device

inputs are compatible with standard CMOS outputs; with pull−up

resistors, they are compatible with LSTTL outputs.

The HC132A can be used to enhance noise immunity or to square up

slowly changing waveforms.

http://onsemi.com

MARKING

DIAGRAMS

Features

PDIP−14

N SUFFIX

CASE 646

MC74HC132AN

AWLYYWWG

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

SOIC−14

D SUFFIX

CASE 751A

HC132AG

AWLYWW

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements as Defined by JEDEC

Standard No. 7A

• Chip Complexity: 72 FETs or 18 Equivalent Gates

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

132A

ALYWG

TSSOP−14

DT SUFFIX

CASE 948G

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

L, WL

Y, YY

= Assembly Location

= Wafer Lot

= Year

13 B4

W, WW = Work Week

G or G

= Pb−Free Package

11 Y4

10 B3

(Note: Microdot may be in either location)

FUNCTION TABLE

GND

Inputs

Output

Figure 1. Pin Assignment

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Publication Order Number:

May, 2013 − Rev. 15

MC74HC132A/D

12 3 4 5 6 7...9

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