Datasheet > NB3V8312C

NB3V8312C

更新时间： 2024-09-27 12:18:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
11页	199K
描述
Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer

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NB3V8312C 数据手册

NB3V8312C

Ultra-Low Jitter, Low Skew

1:12 LVCMOS/LVTTL Fanout

Buffer

The NB3V8312C is a high performance, low skew LVCMOS

fanout buffer which can distribute 12 ultra−low jitter clocks from an

LVCMOS/LVTTL input up to 250 MHz.

http://onsemi.com

The 12 LVCMOS output pins drive 50 W series or parallel

terminated transmission lines. The outputs can also be disabled to a

high impedance (tri−stated) via the OE input, or enabled when High.

The NB3V8312C provides an enable input, CLK_EN pin, which

synchronously enables or disables the clock outputs while in the LOW

state. Since this input is internally synchronized to the input clock,

changing only when the input is LOW, potential output glitching or

runt pulse generation is eliminated.

QFN32

MN SUFFIX

CASE 488AM

LQFP−32

FA SUFFIX

CASE 873A

Separate V

core and V

output supplies allow the output

DDO

buffers to operate at the same supply as the V (V = V ) or

DDO

Q10

Q11

GND

from a lower supply voltage. Compared to single−supply operation,

dual supply operation enables lower power consumption and

output−level compatibility.

CLK_EN

The V core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V,

while the V

output supply voltage can be set to 3.3 V, 2.5 V, or

DDO

1.8 V, with the constraint that V ≥ V

DDO

This buffer is ideally suited for various networking, telecom, server

and storage area networking, RRU LO reference distribution, medical

and test equipment applications.

CLK

Features

• Power Supply Modes:

(Core) / V

(Outputs)

DDO

3.3 V

2.5 V

1.8 V

/ 3.3 V

/ 2.5 V

/ 1.8 V

/ 2.5 V

/ 1.8 V

Figure 1. Simplified Logic Diagram

• 250 MHz Maximum Clock Frequency

• Accepts LVCMOS, LVTTL Clock Inputs

• LVCMOS Compatible Control Inputs

• 12 LVCMOS Clock Outputs

ORDERING AND MARKING INFORMATION

See detailed ordering and shipping information on page 9 of

this data sheet.

• Synchronous Clock Enable

Applications

• Output Enable to High Z State Control

• 150 ps Max. Skew Between Outputs

• Temp. Range −40°C to +85°C

• 32−pin LQFP and QFN Packages

• These are Pb−Free Devices

• Networking

• Telecom

• Storage Area Network

End Products

• Servers

• Routers

• Switches

Publication Order Number:

August, 2013 − Rev. 0

NB3V8312C/D

12 3 4 5 6 7...11

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与NB3V8312C相关器件

型号	品牌	获取价格	描述	数据表
NB3V8312CFAG	ONSEMI	获取价格	Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer
NB3V8312CFAR2G	ONSEMI	获取价格	Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer
NB3V8312CMNG	ONSEMI	获取价格	Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer
NB3V8312CMNR4G	ONSEMI	获取价格	Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer
NB3W1200LMNG	ONSEMI	获取价格	Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle
NB3W1200LMNTXG	ONSEMI	获取价格	Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle
NB3W1900L	ONSEMI	获取价格	Differential 1:19 HCSL-Compatible PushâPull
NB3W1900L_16	ONSEMI	获取价格	3.3 V 100/133 MHz Differential 1:19 HCSL-Comp
NB3W1900L_18	ONSEMI	获取价格	Differential 1:19 HCSL-Compatible PushâPull
NB3W1900LMNG	ONSEMI	获取价格	Differential 1:19 HCSL-Compatible PushâPull

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