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NB3W1200LMNTXG PDF预览

NB3W1200LMNTXG

更新时间: 2024-11-26 12:18:23
品牌 Logo 应用领域
安森美 - ONSEMI PC时钟
页数 文件大小 规格书
26页 230K
描述
Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle

NB3W1200LMNTXG 数据手册

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NB3N1200K, NB3W1200L  
3.3 V 100/133 MHz  
Differential 1:12 HCSL or  
Push-Pull Clock ZDB/Fanout  
Buffer for PCle  
http://onsemi.com  
Description  
The NB3N1200K and NB3W1200L differential clock buffers are  
DB1200Z and DB1200ZL compliant and are designed to work in  
conjunction with a PCIe compliant source clock synthesizer to provide  
pointtopoint clocks to multiple agents. The device is capable of  
®
distributing the reference clocks for Intel QuickPath Interconnect  
64  
1
(Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable  
Memory Interconnect (Intel SMI) applications. The VCO of the  
device is optimized to support 100 MHz and 133 MHz frequency  
operation. The NB3N1200K and NB3W1200L utilize  
pseudoexternal feedback topology to achieve low inputto output  
delay variation. The NB3N1200K is configured with the HCSL buffer  
type, while the NB3W1200L is configured with the lowpower  
NMOS PushPull buffer type.  
QFN64  
MN SUFFIX  
CASE 485DH  
MARKING DIAGRAMS  
1
1
Features  
NB3N  
1200K  
AWLYYWWG  
NB3W  
1200L  
AWLYYWWG  
12 Differential Clock Output Pairs @ 0.7 V  
HCSL Compatible Outputs for NB3N1200K  
LowPower NMOS PushPull Compatible Outputs for NB3W1200L  
Optimized 100 MHz and 133 MHz Operating Frequencies to Meet  
The Next Generation PCIe Gen 2/Gen 3 and Intel QPI Phase Jitter  
DB1200Z and DB1200ZL Compliant  
NB3x1200x= Specific Device Code  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
WL  
YY  
WW  
G
3.3 V 5% Supply Voltage Operation  
FixedFeedback for Lowest InputToOutput Delay Variation  
SMBus Programmable Configurations to Allow Multiple Buffers in a  
Single Control Network  
ORDERING INFORMATION  
PLL Bypass Configurable for PLL or Fanout Operation  
Programmable PLL Bandwidth  
Device  
Package  
Shipping  
NB3N1200KMNG  
NB3N1200KMNTXG  
NB3W1200LMNG  
NB3W1200LMNTXG  
QFN64  
(PbFree)  
260 Units /  
Tray  
2 Trilevel Addresses Selection (9 SMBUS Addresses)  
Individual OE Control Pin for Each of 12 Outputs  
Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant)  
50 ps Max OutputtoOutput Skew Performance  
50 ps Max CycletoCycle Jitter (PLL mode)  
100 ps Input to Output Delay Variation Performance  
QFN 64pin Package, 9 mm x 9 mm  
QFN64  
(PbFree)  
1000 / Tape &  
Reel  
QFN64  
(PbFree)  
260 Units /  
Tray  
QFN64  
(PbFree)  
1000 / Tape &  
Reel  
Spread Spectrum Compatible: Tracks Input Clock Spreading for Low  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
EMI  
0°C to +70°C Ambient Operating Temperature  
These Devices are PbFree and are RoHS Compliant  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
August, 2013 Rev. 0  
NB3N1200K/D  

NB3W1200LMNTXG 替代型号

型号 品牌 替代类型 描述 数据表
NB3W1200LMNG ONSEMI

完全替代

Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle
NB3N1200KMNTXG ONSEMI

类似代替

Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle
NB3N1200KMNG ONSEMI

类似代替

Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle

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