Datasheet > MWS5101AEL3X

MWS5101AEL3X

更新时间： 2024-10-27 22:05:23

品牌	Logo	应用领域
英特矽尔 - INTERSIL		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
7页	44K
描述
256-Word x 4-Bit LSI Static RAM

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MWS5101AEL3X 数据手册

MWS5101,

MWS5101A

256-Word x 4-Bit

LSI Static RAM

March 1997

Features

Description

• Industry Standard Pinout

The MWS5101 and MWS5101A are 256 word by 4-bit static

random access memories designed for use in memory

systems where high speed, very low operating current, and

simplicity in use are desirable. They have separate data

inputs and outputs and utilize a single power supply of 4V to

6.5V. The MWS5101 and MWS5101A differ in input voltage

characteristics (MWS5101A is TTL compatible).

• Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA

at V

= 5V and Cycle Time = 1µs

• Two Chip Select Inputs Simple Memory Expansion

• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)

Battery Voltage

Two Chip Select inputs are provided to simplify system

expansion. An Output Disable control provides Wire-OR

capability and is also useful in common Input/Output

systems by forcing the output into a high impedance state

during a write operation independent of the Chip Select input

condition. The output assumes a high impedance state

when the Output Disable is at high level or when the chip is

deselected by CS1 and/or CS2.

• Output Disable for Common I/O Systems

• Three-State Data Output for Bus Oriented Systems

• Separate Data Inputs and Outputs

• TTL Compatible (MWS5101A)

The high noise immunity of the CMOS technology is

preserved in this design. For TTL interfacing at 5V operation,

excellent system noise margin is preserved by using an

external pull-up resistor at each input.

Pinout

MWS5101, MWS5101A

(PDIP, SBDIP)

TOP VIEW

For applications requiring wider temperature and operating

voltage ranges, the mechanically and functionally equivalent

static RAM, CDP1822 may be used.

The MWS5101 and MWS5101A types are supplied in 22

lead hermetic dual-in-line, sidebrazed ceramic packages (D

sufﬁx), in 22 lead dual-in-line plastic packages (E sufﬁx), and

in chip form (H sufﬁx).

R/W

CSI

O.D.

CS2

DO4

DI4

DO3

DI1

DI3

DO1

DI2

DO2

Ordering Information

MWS5101

MWS5101A

PACKAGE

TEMP. RANGE

250ns

350ns

250ns

350ns

PKG. NO.

E22.4

PDIP

0 C to +70 C

MWS5101EL2

MWS5101ELS

MWS5101AEL2 MWS5101AEL3

Burn-In

MWS5101AEL3X E22.4

MWS5101ADL3 D22.4A

D22.4A

SBDIP

Burn-In

0 C to +70 C

MWS5101DL3X

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 1106.2

6-56

12 3 4 5 6 7

中文翻译

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与MWS5101AEL3X相关器件

型号	品牌	获取价格	描述	数据表
MWS5101DL3X	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM
MWS5101EL2	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM
MWS5101EL2X	RENESAS	获取价格	IC,SRAM,256X4,CMOS,DIP,22PIN,PLASTIC
MWS5101ELS	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM
MWS5114	INTERSIL	获取价格	1024-Word x 4-Bit LSI Static RAM
MWS5114_1	INTERSIL	获取价格	1024-Word x 4-Bit LSI Static RAM
MWS5114D1	INTERSIL	获取价格	1024-Word x 4-Bit LSI Static RAM
MWS5114D1	ROCHESTER	获取价格	Standard SRAM, 1KX4, 300ns, CMOS, CDIP18, DIP-18
MWS5114D2	INTERSIL	获取价格	1024-Word x 4-Bit LSI Static RAM
MWS5114D2X	RENESAS	获取价格	Standard SRAM, 1KX4, 250ns, CMOS, CDIP18,

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