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MWS5101EL2 PDF预览

MWS5101EL2

更新时间: 2024-10-27 22:09:43
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英特矽尔 - INTERSIL /
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7页 44K
描述
256-Word x 4-Bit LSI Static RAM

MWS5101EL2 数据手册

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MWS5101,  
MWS5101A  
256-Word x 4-Bit  
LSI Static RAM  
March 1997  
Features  
Description  
• Industry Standard Pinout  
The MWS5101 and MWS5101A are 256 word by 4-bit static  
random access memories designed for use in memory  
systems where high speed, very low operating current, and  
simplicity in use are desirable. They have separate data  
inputs and outputs and utilize a single power supply of 4V to  
6.5V. The MWS5101 and MWS5101A differ in input voltage  
characteristics (MWS5101A is TTL compatible).  
• Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA  
at V  
= 5V and Cycle Time = 1µs  
DD  
• Two Chip Select Inputs Simple Memory Expansion  
• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)  
Battery Voltage  
Two Chip Select inputs are provided to simplify system  
expansion. An Output Disable control provides Wire-OR  
capability and is also useful in common Input/Output  
systems by forcing the output into a high impedance state  
during a write operation independent of the Chip Select input  
condition. The output assumes a high impedance state  
when the Output Disable is at high level or when the chip is  
deselected by CS1 and/or CS2.  
• Output Disable for Common I/O Systems  
• Three-State Data Output for Bus Oriented Systems  
• Separate Data Inputs and Outputs  
• TTL Compatible (MWS5101A)  
The high noise immunity of the CMOS technology is  
preserved in this design. For TTL interfacing at 5V operation,  
excellent system noise margin is preserved by using an  
external pull-up resistor at each input.  
Pinout  
MWS5101, MWS5101A  
(PDIP, SBDIP)  
TOP VIEW  
For applications requiring wider temperature and operating  
voltage ranges, the mechanically and functionally equivalent  
static RAM, CDP1822 may be used.  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
V
DD  
1
2
A3  
A2  
A1  
A0  
A5  
A6  
A7  
A4  
The MWS5101 and MWS5101A types are supplied in 22  
lead hermetic dual-in-line, sidebrazed ceramic packages (D  
suffix), in 22 lead dual-in-line plastic packages (E suffix), and  
in chip form (H suffix).  
R/W  
CSI  
O.D.  
CS2  
DO4  
DI4  
3
4
5
6
7
8
V
SS  
DO3  
9
DI1  
DI3  
10  
11  
DO1  
DI2  
DO2  
Ordering Information  
MWS5101  
MWS5101A  
PACKAGE  
TEMP. RANGE  
250ns  
350ns  
250ns  
350ns  
PKG. NO.  
E22.4  
o
o
PDIP  
0 C to +70 C  
MWS5101EL2  
MWS5101ELS  
MWS5101AEL2 MWS5101AEL3  
Burn-In  
MWS5101AEL3X E22.4  
MWS5101ADL3 D22.4A  
D22.4A  
o
o
SBDIP  
Burn-In  
0 C to +70 C  
-
MWS5101DL3X  
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 1106.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
6-56  

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