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MTD5P06V

更新时间: 2024-11-20 22:29:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
10页 247K
描述
TMOS POWER FET 5 AMPERES 60 VOLTS RDS(on) = 0.450 OHM

MTD5P06V 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SMALL OUTLINE, R-PSSO-G2Reach Compliance Code:unknown
HTS代码:8541.29.00.95风险等级:5.72
其他特性:AVALANCHE RATED雪崩能效等级(Eas):125 mJ
外壳连接:DRAIN配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:60 V最大漏极电流 (Abs) (ID):5 A
最大漏极电流 (ID):5 A最大漏源导通电阻:0.45 Ω
FET 技术:METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss):60 pF
JESD-30 代码:R-PSSO-G2JESD-609代码:e0
元件数量:1端子数量:2
工作模式:ENHANCEMENT MODE最高工作温度:175 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE极性/信道类型:P-CHANNEL
功耗环境最大值:40 W最大功率耗散 (Abs):40 W
最大脉冲漏极电流 (IDM):18 A认证状态:Not Qualified
子类别:Other Transistors表面贴装:YES
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子位置:SINGLE晶体管应用:SWITCHING
晶体管元件材料:SILICON最大关闭时间(toff):70 ns
最大开启时间(吨):70 nsBase Number Matches:1

MTD5P06V 数据手册

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Order this document  
by MTD5P06V/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
TMOS POWER FET  
5 AMPERES  
P–Channel Enhancement–Mode Silicon Gate  
60 VOLTS  
TMOS V is a new technology designed to achieve an on–resis-  
tance area product about one–half that of standard MOSFETs. This  
new technology more than doubles the present cell density of our  
50 and 60 volt TMOS devices. Just as with our TMOS E–FET  
designs, TMOS V is designed to withstand high energy in the  
avalanche and commutation modes. Designed for low voltage, high  
speed switching applications in power supplies, converters and  
power motor controls, these devices are particularly well suited for  
bridge circuits where diode speed and commutating safe operating  
areas are critical and offer additional safety margin against  
unexpected voltage transients.  
R
= 0.450 OHM  
DS(on)  
TM  
D
New Features of TMOS V  
On–resistance Area Product about One–half that of Standard  
MOSFETs with New Low Voltage, Low R Technology  
CASE 369A–13, Style 2  
DPAK Surface Mount  
G
DS(on)  
Faster Switching than E–FET Predecessors  
S
Features Common to TMOS V and TMOS E–FETS  
Avalanche Energy Specified  
and V Specified at Elevated Temperature  
Static Parameters are the Same for both TMOS V and TMOS E–FET  
Surface Mount Package Available in 16 mm, 13–inch/2500 Unit Tape & Reel,  
Add –T4 Suffix to Part Number  
I
DSS  
DS(on)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
60  
Unit  
Drain–to–Source Voltage  
V
DSS  
Vdc  
Vdc  
Drain–to–Gate Voltage (R  
= 1.0 M)  
Gate–to–Source Voltage — Continuous  
V
DGR  
60  
GS  
V
± 15  
± 25  
Vdc  
Vpk  
GS  
Gate–to–Source Voltage — Non–repetitive (t 10 ms)  
V
GSM  
p
Drain Current — Continuous @ 25°C  
Drain Current — Continuous @ 100°C  
I
I
5
4
18  
Adc  
D
D
Drain Current — Single Pulse (t 10 µs)  
I
Apk  
p
DM  
Total Power Dissipation @ 25°C  
Derate above 25°C  
P
D
40  
0.27  
2.1  
Watts  
W/°C  
Watts  
Total Power Dissipation @ T = 25°C (1)  
A
Operating and Storage Temperature Range  
T , T  
stg  
55 to 175  
125  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — STARTING T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V = 10 Vdc, PEAK I = 5 Apk, L = 10 mH, R = 25 )  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
Thermal Resistance — Junction to Ambient (1)  
R
R
R
3.75  
100  
71.4  
°C/W  
°C  
θJC  
θJA  
θJA  
Maximum Lead Temperature for Soldering Purposes, 1/8from Case for 10 seconds  
T
260  
L
(1) When surface mounted to an FR4 board using the minimum recommended pad size.  
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 1  
Motorola, Inc. 1996  

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