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MT90223AG2 PDF预览

MT90223AG2

更新时间: 2024-01-16 23:40:34
品牌 Logo 应用领域
加拿大卓联 - ZARLINK ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
155页 895K
描述
4/8/16 Port IMA/TC PHY Device

MT90223AG2 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:BGA, BGA384,26X26,40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
应用程序:ATMJESD-30 代码:S-PBGA-B384
JESD-609代码:e1长度:27 mm
湿度敏感等级:3功能数量:1
端子数量:384最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA384,26X26,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5,3.3,5 V
认证状态:Not Qualified座面最大高度:2.28 mm
子类别:ATM/SONET/SDH ICs最大压摆率:0.425 mA
标称供电电压:2.5 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH NETWORK INTERFACE温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:27 mm
Base Number Matches:1

MT90223AG2 数据手册

 浏览型号MT90223AG2的Datasheet PDF文件第1页浏览型号MT90223AG2的Datasheet PDF文件第2页浏览型号MT90223AG2的Datasheet PDF文件第4页浏览型号MT90223AG2的Datasheet PDF文件第5页浏览型号MT90223AG2的Datasheet PDF文件第6页浏览型号MT90223AG2的Datasheet PDF文件第7页 
MT90222/3/4  
Data Sheet  
The device provides up to 8 internal IMA processors and allows for bandwidth scaleability.  
The implementation of IMA as per AF-PHY-0086.001 Inverse Multiplexing for ATM (IMA) Specification Version 1.1  
is divided into hardware and software functions. Hardware functions are implemented in the MT90222/3/4 device  
and software functions are implemented by the IMA Core (Zarlink or user) software. Additional hardware functions  
are included to assist in the collection of statistical information to support MIB implementation.  
Hardware functions that are implemented in the MT90222/3/4 device are:  
Utopia Level 1 or 2 compatible MPHY Interface  
Incoming HEC verification and correction (optional)  
Generation of a new HEC byte  
Format outgoing bytes into multi-vendor TDM formats  
Retrieve ATM Cells from the incoming multi-vendor TDM format  
Perform cell delineation  
Cell pre-processing  
Provide various counters to assist in performance monitoring  
TDM expansion ring to span multiple devices  
Hardware functions that are implemented by the IMA processor in the MT90222/3/4 device are:  
Transmit scheduler (one per IMA group)  
Generation of the TX IMA Data Cell Rate clock  
Generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode and Idle Cells in TC mode; the  
ICP cells are programmed by the user and the Filler and Idle cells are pre-defined  
Perform IMA Frame synchronization  
Retrieve and process Rx ICP cells in IMA Mode  
Management of RX links to be part of the internal re-sequencer when active  
Extraction of RX IMA Data Cell Rate clock  
Verification of delays between links  
Perform re-sequencing of ATM cells using external asynchronous Static RAM  
Can accommodate more than 200 msec of link differential delay depending on the amount of external  
memory  
Provide structured Interrupt scheme to report various events  
3
Zarlink Semiconductor Inc.  

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