Datasheet > MT9040

MT9040

更新时间： 2024-01-15 12:52:37

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
27页	410K
描述
T1/E1 Synchronizer

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技术参数
数据手册

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MT9040 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP, SSOP48,.4	针数：	48
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	JESD-30 代码：	R-PDSO-G48
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP48,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	3.3 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	最大压摆率：	50 mA
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL

MT9040 数据手册

MT9040

T1/E1 Synchronizer

Data Sheet

November 2003

Features

•

Supports AT&T TR62411 and Bellcore GR-1244-

CORE and Stratum 4 timing for DS1 interfaces

Ordering Information

Supports ETSI ETS 300 011, TBR 4, TBR 12 and

TBR 13 timing for E1 interfaces

MT9040AN 48 pin SSOP

Selectable 19.44 MHz, 1.544MHz, 2.048MHz or

8kHz input reference signals

-40°C to +85°C

Provides C1.5, C2, C4, C6, C8, C16, and C19

(STS-3/OC3 clock divided by 8) output clock

signals

Description

The MT9040 T1/E1 System Synchronizer contains a

digital phase-locked loop (DPLL), which provides timing

and synchronization signals for T1 and E1 primary rate

transmission links.

•

Provides 5 different styles of 8 KHz framing

pulses

•

Attenuates wander from 1.9Hz

Fast lock mode

The MT9040 generates ST-BUS clock and framing

signals that are phase locked to either a 19.44 MHz,

2.048MHz, 1.544MHz, or 8kHz input reference.

JTAG Boundary Scan

The MT9040 is compliant with AT&T TR62411 and

Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS

300 011. It will meet the jitter/wander tolerance, jitter

transfer, intrinsic jitter, frequency accuracy and capture

range for these specifications.

Applications

•

Synchronization and timing control for multitrunk

T1 and E1 systems

•

ST-BUS clock and frame pulse source

OSCi

OSCo

FLOCK

LOCK

VDD

VSS

Master Clock

C19o

TCK

TDI

TMS

TRST

TDO

C1.5o

C2o

C4o

C6o

C8o

C16o

F0o

F8o

F16o

RSP

DPLL

IEEE

1149.1a

Output

Interface

Circuit

REF

Input

Impairment

Monitor

TSP

Frequency

Select

MUX

Control State Machine

Feedback

FS1

FS2

RST

Figure 1 - Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

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