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MT9041BP1 PDF预览

MT9041BP1

更新时间: 2024-01-28 18:14:13
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信电信集成电路
页数 文件大小 规格书
21页 484K
描述
Telecom Circuit, 1-Func, CMOS, PQCC28, LEAD FREE, PLASTIC, MS-018AB, LCC-28

MT9041BP1 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.62
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.505 mm湿度敏感等级:3
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):245
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Other Telecom ICs
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.505 mmBase Number Matches:1

MT9041BP1 数据手册

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MT9041B  
T1/E1 System Synchronizer  
DS5059  
ISSUE 4  
June 2000  
Features  
Ordering Information  
Supports AT&T TR62411 and Bellcore  
GR-1244-CORE Stratum 4 Enhanced and  
Stratum 4 timing for DS1 Interfaces  
MT9041BP  
28 Pin PLCC  
-40 to +85 °C  
Supports ETSI ETS 300 011, TBR 4, TBR 12  
and TBR 13 timing for E1 Interfaces  
Description  
Selectable 1.544MHz, 2.048MHz or 8kHz input  
reference signals  
The MT9041B T1/E1 System Synchronizer contains  
a digital phase-locked loop (DPLL), which provides  
timing and synchronization signals for multitrunk T1  
and E1 primary rate transmission links.  
Provides C1.5, C2, C3, C4, C8 and C16 output  
clock signals  
Provides 3 different styles of 8 KHz framing  
pulses  
Attenuates wander from 1.9 Hz  
The MT9041B generates ST-BUS clock and framing  
signals that are phase locked to either a 2.048MHz,  
1.544MHz, or 8kHz input reference.  
Applications  
The MT9041B is compliant with AT&T TR62411 and  
Bellcore GR-1244-CORE Stratum 4 Enhanced,  
Stratum 4, and ETSI ETS 300 011. It will meet the  
jitter tolerance, jitter transfer, intrinsic jitter, frequency  
accuracy, capture range and phase change slope  
requirements for these specifications.  
Synchronization and timing control for  
multitrunk T1 and E1 systems  
ST-BUS clock and frame pulse sources  
VDD  
VSS  
OSCi  
OSCo  
C1.5o  
C3o  
C2o  
C4o  
C8o  
Loop  
Filter  
Phase  
Detector  
REF  
DCO  
Output  
Interface  
Circuit  
C16o  
F0o  
F8o  
F16o  
Mode Select  
Divider  
MS  
RST  
FS1 FS2  
Figure 1 - Functional Block Diagram  
1

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