Datasheet > MT9042CP

MT9042CP

更新时间： 2024-09-20 22:29:47

品牌	Logo	应用领域
MITEL		电信集成电路
页数	文件大小	规格书
28页	116K
描述
Multitrunk System Synchronizer

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中文翻译

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MT9042CP 数据手册

MT9042C

Multitrunk System Synchronizer

Advance Information

DS5144

ISSUE 2

September 1999

Features

Ordering Information

•

Meets jitter requirements for: AT&T TR62411

MT9042CP 28 Pin PLCC

-40^°C to +85^°C

Stratum 3, 4 and Stratum 4 Enhanced for DS1

interfaces; and for ETSI ETS 300 011, TBR 4,

TBR 12 and TBR 13 for E1 interfaces

Description

•

Provides C1.5, C3, C2, C4, C8 and C16 output

clock signals

•

Provides 8kHz ST-BUS framing signals

The MT9042C Multitrunk System Synchronizer

contains a digital phase-locked loop (DPLL), which

provides timing and synchronization signals for

multitrunk T1 and E1 primary rate transmission links.

Selectable 1.544MHz, 2.048MHz or 8kHz input

reference signals

•

Accepts reference inputs from two independent

sources

The MT9042C generates ST-BUS clock and framing

signals that are phase locked to either a 2.048MHz,

1.544MHz, or 8kHz input reference.

Provides bit error free reference switching -

meets phase slope and MTIE requirements

Operates in either Normal, Holdover and

Freerun modes

The MT9042C is compliant with AT&T TR62411

Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300

011. It will meet the jitter tolerance, jitter transfer,

intrinsic jitter, frequency accuracy, holdover

accuracy, capture range, phase slope and MTIE

requirements for these speciﬁcations.

Applications

•

Synchronization and timing control for

multitrunk T1 and E1 systems

•

ST-BUS clock and frame pulse sources

Primary Trunk Rate Converters

TRST

VDD

VSS

Virtual

Refer-

ence

C1.5o

C3o

C2o

C4o

C8o

C16o

F0o

OSCi

TIE

Master

Clock

Corrector

Circuit

DPLL

OSCo

Output

Interface

Circuit

Selected

Refer-

ence

State

Select

PRI

Reference

Select

F8o

F16o

MUX

SEC

Input

Impairment

Monitor

TIE

Corrector

Enable

Reference

Select

State

Select

Feedback

RSEL

LOS1

LOS2

Frequency

Select

MUX

Automatic/Manual

Control State Machine

Guard Time

Circuit

FS1

FS2

MS1

MS2

RST

GTo

GTi

Figure 1 - Functional Block Diagram

12 3 4 5 6 7...28

中文翻译

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与MT9042CP相关器件

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MT9042CP1	MICROCHIP	获取价格	Telecom Circuit, 1-Func, PQCC28
MT9042CP1	ZARLINK	获取价格	Telecom Circuit, 1-Func, CMOS, PQCC28, LEAD FREE, PLASTIC, MS-018AB, LCC-28
MT9042CP1	MICROSEMI	获取价格	Telecom Circuit, 1-Func, CMOS, PQCC28, LEAD FREE, PLASTIC, MS-018AB, LCC-28
MT9042CPR	ZARLINK	获取价格	Telecom Circuit, 1-Func, CMOS, PQCC28, PLASTIC, MS-018AB, LCC-28
MT9042CPR	MICROSEMI	获取价格	Telecom IC, CMOS, PQCC28,
MT9042CPR	MICROCHIP	获取价格	Telecom Circuit, 1-Func, PQCC28
MT9042CPR1	ZARLINK	获取价格	Telecom Circuit, 1-Func, CMOS, PQCC28, LEAD FREE, PLASTIC, MS-018AB, LCC-28
MT9042CPR1	MICROSEMI	获取价格	Telecom Circuit, 1-Func, PQCC28, LEAD FREE, PLASTIC, MS-018AB, LCC-28
MT9043	ZARLINK	获取价格	T1/E1 System Synchronizer
MT9043AN	ZARLINK	获取价格	T1/E1 System Synchronizer