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MT9042CP PDF预览

MT9042CP

更新时间: 2024-02-07 18:49:03
品牌 Logo 应用领域
美国微芯 - MICROCHIP 电信电信集成电路
页数 文件大小 规格书
34页 401K
描述
Telecom Circuit, 1-Func, PQCC28

MT9042CP 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.6
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.505 mm功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Other Telecom ICs最大压摆率:0.06 mA
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11.505 mmBase Number Matches:1

MT9042CP 数据手册

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MT9042C  
Multitrunk System Synchronizer  
Data Sheet  
November 2005  
Features  
Meets jitter requirements for: AT&T TR62411  
Ordering Information  
Stratum 3, 4 and Stratum 4 Enhanced for DS1  
interfaces; and for ETSI ETS 300 011, TBR 4,  
TBR 12 and TBR 13 for E1 interfaces  
MT9042CP  
MT9042CPR 28 Pin PLCC  
MT9042CP1  
28 Pin PLCC  
Tubes  
Tape & Reel  
28 Pin PLCC* Tubes  
Provides C1.5, C3, C2, C4, C8 and C16 output  
clock signals  
MT9042CPR1 28 Pin PLCC* Tape & Reel  
*Pb Free Matte Tin  
Provides 8 kHz ST-BUS framing signals  
-40°C to +85°C  
Selectable 1.544 MHz, 2.048 MHz or 8 kHz  
input reference signals  
Description  
Accepts reference inputs from two independent  
sources  
The MT9042C Multitrunk System Synchronizer  
contains a digital phase-locked loop (DPLL), which  
provides timing and synchronization signals for  
multitrunk T1 and E1 primary rate transmission links.  
Provides bit error free reference switching -  
meets phase slope and MTIE requirements  
Operates in either Normal, Holdover and  
Freerun modes  
The MT9042C generates ST-BUS clock and framing  
signals that are phase locked to either a 2.048 MHz,  
1.544 MHz, or 8 kHz input reference.  
Applications  
The MT9042C is compliant with AT&T TR62411  
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300 011.  
It will meet the jitter tolerance, jitter transfer, intrinsic  
jitter, frequency accuracy, holdover accuracy, capture  
range, phase slope and MTIE requirements for these  
specifications.  
Synchronization and timing control for  
multitrunk T1 and E1 systems  
ST-BUS clock and frame pulse sources  
Primary Trunk Rate Converters  
TRST  
VDD  
VSS  
Virtual  
Refer-  
ence  
C1.5o  
C3o  
C2o  
C4o  
C8o  
C16o  
F0o  
OSCi  
TIE  
Master  
Clock  
Corrector  
Circuit  
DPLL  
OSCo  
Output  
Interface  
Circuit  
Selected  
Refer-  
ence  
State  
Select  
PRI  
Reference  
Select  
F8o  
F16o  
SEC  
MUX  
Input  
Impairment  
Monitor  
TIE  
Correcto  
r Enable  
Reference  
State  
Select  
Feedback  
RSEL  
LOS1  
LOS2  
Frequency  
Select  
MUX  
Automatic/Manual  
Control State Machine  
Guard Time  
Circuit  
FS1  
FS2  
MS1  
MS2  
RST  
GTo  
GTi  
Figure 1 - Functional Block Diagram  
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,  
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.  

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