Datasheet > MT9042AP

MT9042AP

更新时间： 2024-02-21 01:12:21

品牌	Logo	应用领域
MITEL		/
页数	文件大小	规格书
16页	125K
描述
Global Digital Trunk Synchronizer

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技术参数
数据手册

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MT9042AP 技术参数

生命周期：	Active	包装说明：	QCCJ,
Reach Compliance Code：	compliant	风险等级：	5.62
JESD-30 代码：	S-PQCC-J28	长度：	11.505 mm
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
座面最大高度：	4.57 mm	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.505 mm	Base Number Matches：	1

MT9042AP 数据手册

MT9042

Global Digital Trunk Synchronizer

Preliminary Information

ISSUE 1

June 1994

Features

Ordering Information

•

Provides T1 and E1 clocks, and ST-BUS/GCI

MT9042AP

28 Pin PLCC

framing signals locked to an input reference of

either 8 kHz (frame pulse), 1.544 MHz (T1), or

2.048 MHz (E1)

-40^°C to +85^°C

•

Meets AT & T TR62411 and ETSI ETS 300 011

specifications for a 1.544 MHz (T1), or

2.048 MHz (E1) input reference

Description

The MT9042 is a digital phase-locked loop (PLL)

designed to provide timing and synchronization

signals for T1 and E1 primary rate transmission links

that are compatible with ST-BUS/GCI frame

alignment timing requirements. The PLL outputs can

be synchronized to either a 2.048 MHz, 1.544 MHz,

or 8 kHz reference. The T1 and E1 outputs are fully

Provides Time Interval Error (TIE) correction to

suppress input reference rearrangement

transients

•

Typical unfiltered intrinsic output jitter is

0.013 UI peak-to-peak

Jitter attenuation of 15 dB @ 10 Hz,

34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz

compliant with AT & T TR62411 (ACCUNET T1.5)

and ETSI ETS 300 011 intrinsic jitter and jitter

Low power CMOS technology

transfer

specifications,

respectively,

when

synchronized to primary reference input clock rates

of either 1.544 MHz or 2.048 MHz.

Applications

The PLL also provides additional high speed output

clocks at rates of 3.088 MHz, 4.096 MHz, 8.192

MHz, and 16.384 MHz for backplane synchro-

nization.

•

Synchronization and timing control for T1 and

E1 digital transmission links

•

ST-BUS clock and frame pulse sources

Primary Trunk Rate Converters

VDD

VSS

TRST

MCLKo

MCLKi

RST

C1.5

C16

PRI

Reference

Select

MUX

TIE

Corrector

PLL

Interface

Circuit

SEC

F0o

FP8-STB

FP8-GCI

RSEL

LOSS1

LOSS2

Automatic State

Machine

Divider

FSEL1

GTo GTi

MS1 MS2

FSEL2

Figure 1 - Functional Block Diagram

3-97

12 3 4 5 6 7...16

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