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MS81V04160-30TB PDF预览

MS81V04160-30TB

更新时间: 2024-01-29 03:35:30
品牌 Logo 应用领域
冲电气 - OKI 先进先出芯片
页数 文件大小 规格书
22页 111K
描述
Dual FIFO (262,214-word x 8-Bits) x 2

MS81V04160-30TB 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:TFQFP,针数:100
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.77
最长访问时间:30 ns周期时间:30 ns
JESD-30 代码:S-PQFP-G100长度:14 mm
内存密度:2097152 bit内存宽度:8
功能数量:2端子数量:100
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX8
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH并行/串行:SERIAL
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

MS81V04160-30TB 数据手册

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OKI Semiconductor  
MS81V04160  
REVISION1 1999.4.15  
Dual FIFO (262,214-word x 8-Bits) x 2  
GENERAL DESCRIPTION  
The MS81V04160 is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO  
(First-In First-Out) memories which were designed for 256k x 8-bit high-speed  
asynchronous read/write operation.  
The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in  
common. The MS81V04160, functionally compatible with Oki's 2Mb FIFO memory  
(MSM51V8222A), can be used as a x16 configuration FIFO.  
The MS81V04160 is a field memory for wide or low end use in general commodity TVs and  
VTRs exclusively and is not designed for high end use in professional graphics systems,  
which require long term picture storage, data storage, medical use and other storage  
systems.  
The MS81V04160 provides independent control clocks to support asynchronous read and  
write operations. Different clock rates are also supported, which allow alternate data rates  
between write and read data streams.  
The MS81V04160 provides high speed FIFO (First-in First-out) operation without external  
refreshing: MS81V04160 refreshes its DRAM storage cells automatically, so that it appears  
fully static to the users.  
Moreover, fully static type memory cells and decoders for serial access enable the refresh  
free serial access operation, so that serial read and/or write control clock can be halted  
high or low for any duration as long as the power is on. Internal conflicts of memory access  
and refreshing operations are prevented by special arbitration logic.  
The MS81V04160’s function is simple, and similar to a digital delay device whose delay-bit-  
length is easily set by reset timing. The delay length and the number of read delay clocks  
between write and read, is determined by externally controlled write and read reset timings.  
Additional SRAM serial registers, or line buffers for the initial access of 256 x 16-bit enable  
high speed first-bit-access with no clock delay just after the write or read reset timings.  
Additionally, the MS81V04160 has a write mask function or input enable function (IE), and  
read- data skipping function or output enable function (OE). The differences between write  
enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE)  
are that WE and RE can stop serial write/read address increments, but IE and OE cannot  
stop the increment, when write/read clocking is continuously applied to MS81V04160. The  
input enable (IE) function allows the user to write into selected locations of the memory  
only, leaving the rest of the memory contents unchanged.This facilitates data processing to  
display a “picture in picture” on a TV screen.  
1

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Dual FIFO (262,214 Words 】 8 Bits) 】 2
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Dual FIFO (262,214 Words × 8 Bits) × 2
MS81V04166-30TB OKI

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FIFO, 256KX8, 30ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
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MS81V04166A-25TB OKI

获取价格

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MS81V04166A-XXTB OKI

获取价格

Dual FIFO (262,214 Words 】 8 Bits) 】 2