Datasheet > MPC962309EF-1R2

MPC962309EF-1R2

更新时间： 2024-11-12 12:02:43

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	500K
描述
Low-Cost, 3.3V Zero Delay Buffer

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MPC962309EF-1R2 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	系列：	962309
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	9.9 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.008 A
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	16
实输出次数：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	传播延迟（tpd）：	8.7 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.25 ns
座面最大高度：	1.75 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm	最小 fmax：	133.33 MHz

MPC962309EF-1R2 数据手册

Low-Cost, 3.3V Zero Delay Buffer

MPC962305

NRND

DATASHEET

NRND – Not Recommend for New Designs

The MPC962309 is a zero delay buffer designed to distribute high-speed

clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one

reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin

version of the MPC962309 which drives five outputs with one reference input.

The -1H versions of these devices have higher drive than the -1 devices and can

operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which

lock to an input clock presented on the REF pin. The PLL feedback is on-chip and

is obtained from the CLOCKOUT pad.

MPC962305

MPC962309

EF SUFFIX

8-LEAD SOIC PACKAGE

Pb-FREE PACKAGE

CASE 751-06

Features

EJ SUFFIX

8-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE

CASE 948J-01

•

1:5 LVCMOS zero-delay buffer (MPC962305)

1:9 LVCMOS zero-delay buffer (MPC962309)

Zero input-output propagation delay

Multiple low-skew outputs

EF SUFFIX

16-LEAD SOIC PACKAGE

Pb-FREE PACKAGE

CASE 751B-05

250 ps max output-output skew

700 ps max device-device skew

Supports a clock I/O frequency range of 10 MHz to 133 MHz,

compatible with CPU and PCI bus frequencies

•

Low jitter, 200 ps max cycle-cycle, and compatible with Pentium^®based

systems

•

Test Mode to bypass PLL (MPC962309 only. See Table 3)

EJ SUFFIX

16-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE

CASE 948F-01

8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin

TSSOP package (MPC962309), all Pb-free

•

Single 3.3 V supply

Ambient temperature range: –40C to +85C

Compatible with the CY2305, CY23S05, CY2309, CY23S09

Spread spectrum compatible

Not Recommend for New Designs

Use replacement part IDT2305

•

The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank

B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs

for chip and system testing purposes.

The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During

this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 A of current draw for the device. The

PLL shuts down in one additional case as shown in Table 3.

Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this

situation, the difference between the output skews of two devices will be less than 700 ps.

All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to

be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.

The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information

page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and

MPC962309-1H, are available to provide faster rise and fall times of the base device.

Pentium II is a trademark of Intel Corporation.

MPC962305 REVISION 8 JANUARY 8, 2013

12 3 4 5 6 7...18

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与MPC962309EF-1R2相关器件

型号	品牌	获取价格	描述	数据表
MPC962309EJ-1H	IDT	获取价格	Low-Cost, 3.3V Zero Delay Buffer
MPC962309EJ-1H	NXP	获取价格	962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 4.4
MPC962309EJ-1HR2	IDT	获取价格	Low-Cost, 3.3V Zero Delay Buffer
MPC962309EJ-1HR2	NXP	获取价格	962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 4.4
MPC9653	MOTOROLA	获取价格	3.3V 1:8 LVCMOS PLL CLOCK GENERATOR
MPC9653AAC	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FRE
MPC9653AAC	IDT	获取价格	PLL Based Clock Driver, 9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9653AACR2	IDT	获取价格	PLL Based Clock Driver, 9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9653AACR2	MOTOROLA	获取价格	Clock Driver, CMOS, PQFP32,
MPC9653AFA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32

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