Datasheet > MPC9653AACR2

MPC9653AACR2

更新时间： 2024-09-23 19:36:03

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
12页	405K
描述
PLL Based Clock Driver, 9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, LEAD FREE, PLASTIC, LQFP-32

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MPC9653AACR2 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	7 X 7 MM, LEAD FREE, PLASTIC, LQFP-32	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.22
系列：	9653	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e3
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.024 A	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	8
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP32,.35SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
Prop。Delay @ Nom-Sup：	7 ns	传播延迟（tpd）：	7 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.15 ns
座面最大高度：	1.6 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	7 mm
最小 fmax：	50 MHz	Base Number Matches：	1

MPC9653AACR2 数据手册

3.3 V 1:8 LVCMOS PLL Clock Generator

MPC9653A

NRND

DATASHEET

NRND – Not Recommend for New Designs

The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and

zero-delay buffer targeted for high performance low-skew clock distribution in

mid-range to high-performance telecom, networking and computing applications.

With output frequencies up to 125 MHz and output skews less than 150 ps the

device meets the needs of the most demanding clock applications.

MPC9653A

Features

•

1:8 PLL based low-voltage clock generator

Supports zero-delay operation

LOW VOLTAGE

3.3 V LVCMOS 1:8

PLL CLOCK GENERATOR

3.3 V power supply

Generates clock signals up to 125 MHz

PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz

Maximum output skew of 150 ps

Differential LVPECL reference clock input

External PLL feedback

Drives up to 16 clock lines

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

32-lead LQFP packaging

32-lead Pb-free Package Available

Ambient temperature range 0C to +70C

Pin and function compatible to the MPC953 and MPC9653

NRND – Not Recommend for New Designs

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

The MPC9653A utilizes PLL technology to frequency lock its outputs onto an

input reference clock. Normal operation of the MPC9653A requires the connec-

tion of the QFB output to the feedback input to close the PLL feedback path (ex-

ternal feedback). With the PLL locked, the output frequency is equal to the

reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5 MHz or 50 to 125 MHz. The

two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine

the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running

at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high

frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F_ref= 36.25 MHz.

The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use

as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se-

lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by-

pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes

the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close

the phase locked loop, enabling the PLL to recover to normal operation.

The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50  transmission

lines. For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an

effective fanout of 1:16. The device is packaged in a 7x7 mm²32-lead LQFP package.

MPC9653A REVISION 4 JANUARY 8, 2013

12 3 4 5 6 7...12

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与MPC9653AACR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9653AFA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MPC9653AFA	IDT	获取价格	PLL Based Clock Driver, 9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9653FA	NXP	获取价格	IC,1:8 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC9653FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MPC9653FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MPC9658	MOTOROLA	获取价格	3.3V 1:10 LVCMOS PLL Clock Generator
MPC9658AC	NXP	获取价格	9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9658ACR2	IDT	获取价格	PLL Based Clock Driver, 9658 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9658ACR2	NXP	获取价格	9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9658FA	IDT	获取价格	PLL Based Clock Driver, 9658 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32

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