MPC9259D

更新时间： 2024-01-17 18:05:59

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
12页	297K
描述
900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MPC9259D 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.52
Is Samacsys：	N	JESD-30 代码：	S-PQFP-G32
长度：	7 mm	端子数量：	32
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	900 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	主时钟/晶体标称频率：	20 MHz
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	7 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

MPC9259D 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9259/D

Rev 0, 12/2002

The MPC9259 is a 3.3V compatible, PLL based clock synthesizer

targeted for high performance clock generation in mid-range to

high-performance telecom, networking and computing applications. With

output frequencies from 50 MHz to 900 MHz and the support of differential

LVDS output signals the device meets the needs of the most demanding

clock applications.

900 MHZ LOW VOLTAGE

CLOCK SYNTHESIZER

Features

• 50 MHz to 900 MHz synthesized clock output signal

• Differential LVDS output

• LVCMOS compatible control inputs

• On-chip crystal oscillator for reference frequency generation

• Alternative LVCMOS compatible reference input

• 3.3V power supply

• Fully integrated PLL

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A

• Minimal frequency overshoot

• Serial 3-wire programming interface

• Parallel programming interface for power-up

• 32 Pin LQFP Package

• SiGe Technology

• Ambient temperature range 0°C to + 70° C

Functional Description

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the

internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range

of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal

oscillator frequency f , the PLL feedback-divider M and the PLL post-divider N determine the output frequency.

XTAL

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by

adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock.

The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be

programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division

ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]

inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes

valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control

inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the

S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this

document. The configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input.

See the programming section for more information. The TEST output reflects various internal node values, and is controlled by

the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST

output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked

by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the

PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

For More Information On This Product,

Motorola, Inc. 2002

Go to: www.freescale.com

12 3 4 5 6 7...12

中文翻译

下载PDF

与MPC9259D相关器件

型号	品牌	获取价格	描述	数据表
MPC9259FA	FREESCALE	获取价格	900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER
MPC9259FA	MOTOROLA	获取价格	900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER
MPC926508SD	NXP	获取价格	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,SSOP,20PIN,PLASTIC
MPC926508SD	IDT	获取价格	Processor Specific Clock Generator, 133.33MHz, CMOS, PDSO20, 0.150 INCH, SSOP-20
MPC926508SD	MOTOROLA	获取价格	Processor Specific Clock Generator, 133.33MHz, CMOS, PDSO20, SSOP-20
MPC9299FA	MOTOROLA	获取价格	Clock Generator, 400MHz, CMOS, PQFP32, LQFP-32
MPC9299FN	MOTOROLA	获取价格	400 MHz, OTHER CLOCK GENERATOR, PQCC28, PLASTIC, LCC-28
MPC930	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC930FA	MOTOROLA	获取价格	Processor Specific Clock Generator, 140MHz, CMOS, PQFP32, PLASTIC, TQFP-32
MPC930FAR2	MOTOROLA	获取价格	140MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32, TQFP-32

与MPC9259D相关文章

MBRS340T3G手册解读：参数说明、产品特性及应用
2024-06-28

5
PMOS管背靠背连接：串联还是并联？
2024-06-28

6
高压电解电容的分类与选型策略
2024-06-28

7
数码管：基本概念、分类、技术发展及市场趋势
2024-06-27

12

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC9259D

MPC9259D 技术参数

MPC9259D 数据手册

与MPC9259D相关器件

与MPC9259D相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC9259D

MPC9259D 技术参数

MPC9259D 数据手册

与MPC9259D相关器件

与MPC9259D相关文章

您还可以找

您在本页遇到什么问题？