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MPC5123

更新时间： 2024-09-16 05:49:51

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e300 Power Architecture processor core

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MPC5123 数据手册

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC5121E

Rev. 4, 01/2010

MPC5121E/MPC5123

516 TEPBGA

27 mm x 27 mm

MPC5121E/MPC5123

Data Sheet

The MPC5121e/MPC5123 integrates a high performance

e300 CPU core based on the Power Architecture Technology

with a rich set of peripheral functions focused on

communications and systems integration.

• On-chip temperature sensor

• IIM – IC Identification module

Figure 1 shows a simplified MPC5121e/MPC5123 block

diagram.

Major features of the MPC5121e/MPC5123 are:

• e300 Power Architecture processor core

• Power modes include doze, nap, sleep, deep sleep, and

hibernate

• AXE – Auxiliary Execution Engine

• MBX Lite – 2D/3D graphics engine (not available in

MPC5123)

• DIU – Display interface unit

• DDR1, DDR2, and LPDDR/mobile-DDR SDRAM

memory controller

• MEM – 128 Kbyte on-chip SRAM

• USB 2.0 OTG controller with integrated physical layer

(PHY)

• DMA subsystem

• EMB – Flexible multi-function external memory bus

interface

• NFC – NAND flash controller

• LPC – LocalPlus interface

• 10/100Base Ethernet

• PCI interface, version 2.3

• PATA – Parallel ATA integrated development environment

(IDE) controller

• SATA – Serial ATA controller with integrated physical

layer (PHY)

• SDHC – MMC/SD/SDIO card host controller

• PSC – Programmable serial controller

• I C – inter-integrated circuit communication interfaces

• S/PDIF – Serial audio interface

• CAN – Controller area network

• BDLC – J1850 interface

• VIU – Video Input, ITU-656 compliant

• RTC – On-Chip real-time clock

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

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