Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5200BDS
Rev. 4, 02/2010
MPC5200B Data Sheet
TEPBGA–272
27 mm x 27 mm
Key features are shown below.
• MPC603e series e300 core
– Superscalar architecture
– Full duplex SPI mode
– IrDA mode from 2400 bps to 4 Mbps
• Fast Ethernet Controller (FEC)
– Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE
802.3 MII, 10 Mbps 7-wire interface
• Universal Serial Bus Controller (USB)
– USB Revision 1.1 Host
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o
– 760 MIPS at 400 MHz (–40 C to +85 C)
– 16 KB Instruction cache, 16 KB Data cache
– Double precision FPU
– Instruction and Data MMU
– Standard and Critical interrupt capability
• SDRAM / DDR Memory Interface
– Up to 133 MHz operation
– Open Host Controller Interface (OHCI)
– Integrated USB Hub, with two ports.
• Two Inter-Integrated Circuit Interfaces (I C)
2
– SDRAM and DDR SDRAM support
– 256 MB addressing range per CS, two CS available
– 32-bit data bus
• Serial Peripheral Interface (SPI)
• Dual CAN 2.0 A/B Controller (MSCAN)
– Implementation of version 2.0A/B CAN protocol
– Standard and extended data frames
• J1850 Byte Data Link Controller (BDLC)
• J1850 Class B data communication network interface
compatible and ISO compatible for low speed (<125 kbps)
serial data communications in automotive applications.
• Supports 4X mode, 41.6 kbps
– Built-in initialization and refresh
• Flexible multi-function External Bus Interface
– Supports interfacing to ROM/Flash/SRAM memories or
other memory mapped devices
– 8 programmable Chip Selects
– Non-multiplexed data access using 8-/16-/32-bit databus
with up to 26-bit address
• In-frame response (IFR) types 0, 1, 2, and 3 supported
• Systems level features
– Short or Long Burst capable
– Multiplexed data access using 8-/16-/32-bit databus
with up to 25-bit address
• Peripheral Component Interconnect (PCI) Controller
– Version 2.2 PCI compatibility
– Interrupt Controller supports four external interrupt
request lines and 47 internal interrupt sources
– GPIO/Timer functions
Up to 56 total GPIO pins that support a variety of
interrupt/WakeUp capabilities.
Eight GPIO pins with timer capability supporting input
capture, output compare, and pulse width modulation
(PWM) functions
– PCI initiator and target operation
– 32-bit PCI Address/Data bus
– 33 and 66 MHz operation
– PCI arbitration function
• ATA Controller
– Real-time Clock with one-second resolution
– Systems Protection (watch dog timer, bus monitor)
– Individual control of functional block clock sources
– Power management: Nap, Doze, Sleep, Deep Sleep
modes
– Version 4 ATA compatible external interface—IDE Disk
Drive connectivity
• BestComm DMA subsystem
– Intelligent virtual DMA Controller
– Dedicated DMA channels to control peripheral
reception and transmission
– Support of WakeUp from low power modes by different
sources (GPIO, RTC, CAN)
– Local memory (SRAM 16 KB)
• 6 Programmable Serial Controllers (PSC)
– UART or RS232 interface
• Test/Debug features
– JTAG (IEEE 1149.1 test access port)
– Common On-chip Processor (COP) debug port
• On-board PLL and clock generation
– CODEC interface for Soft Modem, Master/Slave
2
CODEC Mode, I S and AC97
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2008, 2010. All rights reserved.