Datasheet > MPC5510

MPC5510

更新时间： 2024-11-26 05:49:51

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器 PC
页数	文件大小	规格书
54页	436K
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MPC5510 Microcontroller Family Data Sheet

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MPC5510 数据手册

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5510

Rev. 2, 12/2008

MPC5510

LQFP–144

QFN12

MMAAPPBBGGAA––220285

20 mm x 20 mm

##_mm_x_##mm

1175mmmmxx1175mmmm

LQFP–176

24 mm x 24 mm

SOT-343R

##_mm_x_##mm

PKG-TBD

MPC5510 Microcontroller

Family Data Sheet

## mm x ## mm

TBD

MPC5510 Family Features

• Up to 144 configurable general purpose pins supporting

input and output operations and 3.0V through 5.5V supply

levels

• Real-time counter (RTC_API) with clock source from

external 32-kHz crystal oscillator, internal 32-kHz or

16-MHz oscillator and supporting wake-up with selectable

1-second resolution and > 1-hour timeout, or 1-millisecond

resolution with maximum timeout of one second

• Up to eight periodic interrupt timers (PIT) with 32-bit

counter resolution

• Single issue, 32-bit CPU core complex (e200z1)

– Compliant with the Power Architecture™ embedded

category

– Includes an instruction set enhancement allowing

variable length encoding (VLE) for code size footprint

reduction. With the optional encoding of mixed 16-bit

and 32-bit instructions, it is possible to achieve

significant code size footprint reduction.

• Up to 1.5-Mbyte on-chip flash with flash control unit

(FCU)

• Up to 80 Kbytes on-chip SRAM

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003 Class Two Plus standard

• Device/board test support per Joint Test Action Group

(JTAG) of IEEE (IEEE 1149.1)

• On-chip voltage regulator (VREG) for regulation of 5V

input to 1.5V and 3.3V internal supply levels

• Optional e200z0, second Power Architecture based I/O

processor with VLE instruction set

• Memory protection unit (MPU) with up to sixteen region

descriptors and 32-byte region granularity

• Interrupt controller (INTC) capable of handling

selectable-priority interrupt sources

• Frequency modulated Phase-locked loop (FMPLL)

• Crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters

• 16-channel enhanced direct memory access controller

(eDMA)

• Optional FlexRAY controller

• Optional external bus interface (EBI) module

• Boot assist module (BAM) supports internal flash

programming via a serial link (CAN or SCI)

• Timer supports input/output channels providing a range of

16-bit input capture, output compare, and pulse width

modulation functions (eMIOS200)

• Up to 40-channel 12-bit analog-to-digital converter (ADC)

• Up to four serial peripheral interface (DSPI) modules

• Media Local Bus (MLB) emulation logic (works with two

DSPIs, the e200z0, the eDMA, and system RAM to create

a 3-pin or 5-pin 256Fs MLB protocol)

• Up to eight serial communication interface (eSCI) modules

• Up to six enhanced full CAN (FlexCAN) modules with

configurable buffers

• One inter IC communication interface (I C) module

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Preliminary—Subject to Change Without Notice

12 3 4 5 6 7...54

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MPC5514G(144LQFP)	NXP	获取价格	MPC5514G(144LQFP)
MPC5514GCVL	NXP	获取价格	MPC5514GCVL
MPC5514GMAG	NXP	获取价格	MPC5514GMAG
MPC5514GMVL	NXP	获取价格	MPC5514GMVL
MPC5515S(144LQFP)	NXP	获取价格	MPC5515S(144LQFP)
MPC5515S(176LQFP)	NXP	获取价格	MPC5515S(176LQFP)
MPC5516EMAG	NXP	获取价格	MPC5516EMAG
MPC5516EMVL	NXP	获取价格	MPC5516EMVL
MPC5516EVAG	NXP	获取价格	MPC5516EVAG
MPC5516GCAG	NXP	获取价格	MPC5516GCAG

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