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MPC5200CBV400 PDF预览

MPC5200CBV400

更新时间: 2024-11-22 22:28:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 微控制器和处理器外围集成电路微处理器PC时钟
页数 文件大小 规格书
76页 1363K
描述
MPC5200 Hardware Specifications

MPC5200CBV400 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA, BGA272,20X20,50针数:272
Reach Compliance Code:unknownECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.56
Is Samacsys:N地址总线宽度:32
边界扫描:YES最大时钟频率:35 MHz
外部数据总线宽度:32格式:FIXED POINT
集成缓存:YESJESD-30 代码:S-PBGA-B272
长度:27 mm低功率模式:YES
端子数量:272最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:2.65 mm速度:400 MHz
最大供电电压:1.58 V最小供电电压:1.42 V
标称供电电压:1.5 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:27 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

MPC5200CBV400 数据手册

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Freescale Semiconductor, Inc.  
MPC5200/D  
Rev. 2, 5/2004  
MPC5200 Hardware  
Specifications  
Topic  
Page  
NOTE:  
The information in this document is subject to  
1
2
3
Overview ......................................1  
change. For the latest data on the MPC5200, visit  
www.mobilegt.com and proceed to the MPC5200  
Product Summary Page.  
Features .......................................1  
Electrical and Thermal  
Characteristics..............................5  
4
5
6
7
Package Description ..................60  
System Design Information ........69  
Ordering Information ..................74  
Document Revision History........75  
1
Overview  
The MPC5200 integrates a high performance MPC603e series G2_LE core with a  
rich set of peripheral functions focused on communications and systems  
integration. The G2_LE core design is based on the PowerPC® core architecture.  
MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates  
routine maintenance of peripheral functions from the embedded G2_LE core. The  
MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus  
Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers  
(PSC), I2C, SPI, CAN, J1850, Timers, and GPIOs.  
2
Features  
Key features are shown below.  
MPC603e series G2_LE core  
— Superscalar architecture  
— 760 MIPS at 400 MHz (-40 to +85 oC)  
— 16 k Instruction cache, 16 k Data cache  
— Double precision FPU  
— Instruction and Data MMU  
— Standard and Critical interrupt capability  
SDRAM / DDR Memory Interface  
— up to 132-MHz operation  
— SDRAM and DDR SDRAM support  
— 256-MByte addressing range per CS, two CS available  
— 32-bit data bus  
— Built-in initialization and refresh  
Flexible multi-function External Bus Interface  
— Supports interfacing to ROM/Flash/SRAM memories or other memory  
mapped devices  
For More Information On This Product,  
Go to: www.freescale.com  

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