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MPC5121VY400B PDF预览

MPC5121VY400B

更新时间: 2024-10-30 07:03:19
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MPC5121VY400B 数据手册

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Freescale Semiconductor  
Data Sheet: Advance Information  
Document Number: MPC5121E  
Rev. 1, 10/2008  
MPC5121E/MPC5123  
TEPBGA  
27 mm x 27 mm  
MPC5121E/MPC5123  
Data Sheet  
The MPC5121e/MPC5123 integrates a high performance  
e300 CPU core based on the Power Architecture Technology  
with a rich set of peripheral functions focused on  
communications and systems integration.  
Major features of the MPC5121e/MPC5123 are:  
• e300 Power Architecture processor core (enhanced version  
of the MPC603e core), operates up to 400 MHz  
• Power modes include doze, nap, sleep, deep sleep, and  
hibernate  
• AXE – fully programmable, 200 MHz 32-bit RISC core for  
real-time acceleration tasks, such as audio.  
• MBX Lite – 2D/3D graphics engine with PowerVR vector  
processing (only in MPC5121e, not in MPC5123)  
• DIU – Display interface unit  
• DDR1, DDR2, and low-power mobile DDR (LPDDR)  
SDRAM memory controller  
• USB 2.0 OTG controller with integrated physical layer  
(PHY)  
• DMA subsystem  
• EMB – Flexible multi-function external memory bus  
interface  
• NFC – NAND flash controller  
• 10/100Base Ethernet  
• PCI interface, version 2.3  
PATA Parallel ATA integrated development environment  
(IDE) controller  
• SATA Serial ATA controller with integrated physical  
layer (PHY)  
• SDHC – MMC/SD/SDIO card host controller  
• PSC – Programmable serial controller  
• S/PDIF – Serial audio interface  
• CAN – Controller area network  
• BDLC – J1850 interface  
• VIU – Video Input, ITU-656 complient  
Figure 1 shows a simplified MPC5121e/MPC5123 block  
diagram.  
This document contains information on a product under development. Freescale reserves the  
right to change or discontinue this product without notice.  
© Freescale Semiconductor, Inc., 2008. All rights reserved.  
Preliminary  

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