Datasheet > MG2RT

MG2RT

更新时间： 2024-09-15 12:47:19

品牌	Logo	应用领域
爱特美尔 - ATMEL		栅
页数	文件大小	规格书
13页	211K
描述
Rad Tolerant 350K Used Gates 0.5 Î¼m CMOS Sea of Gates

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MG2RT 数据手册

Features

• Full Range of Matrices with up to 480K Gates

• 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates

• RAM and DPRAM Compilers

• Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)

• 3 and 5 Volts Operation; Single or Dual Supply Mode

• High Speed Performances:

– 450 ps Max NAND2 Propagation Delay at 4.5V, 720 ps at 2.7V and FO = 5

– Min 610 MHz Toggle Frequency at 4.5V, 320 MHz at 2.7V

• Programmable PLL Available upon Request

• High System Frequency Skew Control through Clock Tree Synthesis Software

• Low Power Consumption:

Rad Tolerant

350K Used Gates

0.5 µm CMOS

Sea of Gates

– 1.96 µW/Gate/MHz at 5V

– 0.6 µW/Gate/MHz at 3V

• Integrated Power On Reset

• Matrices with a Max of 484 Fully Programmable Pads

• Standard 3, 6, 12 and 24 mA I/Os

• Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator

• CMOS/TTL/PCI Interface

• ESD (2 kV) and Latch-up Protected I/O

MG2RT

• High Noise and EMC Immunity:

– I/O with Slew Rate Control

– Internal Decoupling

– Signal Filtering between Periphery and Core

– Application Dependent Supply Routing and Several Independant Supply Sources

• Wide Selection of MQFPs and MCGA Packages up to 472 Pins

• Delivery in Die Form with 94.6 µm Pad Pitch

• Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout,

Power Management

• Cadence^®, Mentor^®, Vital^®and Synopsys^®Reference Platforms

• EDIF and VHDL Reference Formats

• Available in Military and Space Quality Grades (SCC, MIL-PRF-38535)

• No Single Event Latch-up below an LET threshold of 80MeV/mg/cm²

• Tested up to a Total Dose of 60 Krad (Si) according to MIL STD 883 Method 1019

• QML Q and V with SMD 5962-00B02

Description

The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays

up to 480K gates cover most system integration needs. The MG2RT is manufactured

using a 0.5 micron drawn, 3 metal layer CMOS process, called SCMOS 3/2RT.

The base cell architecture of the MG2RT series provides high routability of logic with

extremely dense compiled memories: RAM and DPRAM. ROM can be generated

using synthesis tools.

Accurate control of clock distribution can be achieved by PLL hardware and CTS

(Clock Tree Synthesis) software. New noise prevention techniques are applied in the

array and in the periphery: three or more independent supplies, internal decoupling,

customiszation dependent supply routing, noise filtering, skew controlled I/Os, low

swing differential I/Os, all contribute to improve the noise immunity and reduce the

emission level.

The MG2RT is supported by an advanced software environment based on industry

standards linking proprietary and commercial tools. Verilog, Modelsym and Design

Compiler are the reference front-end tools. Floor planning associated with timing-

driven layout provides a short back-end cycle.

12 3 4 5 6 7...13

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与MG2RT相关器件

型号	品牌	获取价格	描述	数据表
MG2RTP	ATMEL	获取价格	Rad Hard 190K Used Gates 0.5 μm CMOS Sea of G
MG2-S-30-420-1-BB2-A-C	Carling Technologies	获取价格	Magnetic Circuit Breaker,
MG2-S-94-480-1-JC5-2-C	Carling Technologies	获取价格	Magnetic Circuit Breaker,
MG-3000-B-9V-R	AMPHENOL	获取价格	Peizoresistive Sensor,
MG-300-B-9V-F-R	AMPHENOL	获取价格	Peizoresistive Sensor,
MG300G1UL1	TOSHIBA	获取价格	TRANSISTOR 300 A, 450 V, NPN, Si, POWER TRANSISTOR, 2-109A1A, 5 PIN, BIP General Purpose P
MG300H1FL1	TOSHIBA	获取价格	TRANSISTOR 300 A, 550 V, NPN, Si, POWER TRANSISTOR, 2-80D1A, 4 PIN, BIP General Purpose Po
MG300H1UL1	TOSHIBA	获取价格	TRANSISTOR 300 A, 550 V, NPN, Si, POWER TRANSISTOR, 2-109A1A, 5 PIN, BIP General Purpose P
MG300H1US1	TOSHIBA	获取价格	TRANSISTOR 300 A, 500 V, N-CHANNEL IGBT, 2-109A4A, 4 PIN, Insulated Gate BIP Transistor
MG300HF065TLC2	YANGJIE	获取价格	C2

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