Datasheet > 存储 > SRAM> MCM69R736AZP6R

MCM69R736AZP6R

更新时间： 2024-11-10 22:20:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
20页	228K
描述
4M Late Write HSTL

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MCM69R736AZP6R 数据手册

Order this document

by MCM69R736A/D

SEMICONDUCTOR TECHNICAL DATA

MCM69R736A

MCM69R818A

Advance Information

4M Late Write HSTL

TheMCM69R736A/818Aisa4megabitsynchronouslatewritefaststaticRAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM69R818A

organized as 256K words by 18 bits, and the MCM69R736A organized as 128K

words by 36 bits wide are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential CK clock inputs control the timing of read/write operations of

the RAM. At the rising edge of the CK clock all addresses, write enables, and

synchronous selects are registered. An internal buffer and special logic enable

the memory to accept write data on the rising edge of the CK clock a cycle after

address and control signals. Read data is driven on the rising edge of the CK

clock also.

ZP PACKAGE

PBGA

CASE 999–01

TheRAMusesHSTLinputsandoutputs. Theadjustableinputtrip–point(V

)

ref

and output voltage (V

) gives the system designer greater flexibility in

DDQ

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

Single 3.3 V +10%, – 5% Operation

HSTL – I/O (JEDEC Standard JESD8–6 Class I Compatible)

HSTL – User Selectable Input Trip–Point

HSTL – Compatible Programmable Impedance Output Drivers

Asynchronous Output Enable

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x 18 or x 36 organization

MCM69R736A/818A–5 = 5 ns

MCM69R736A/818A–6 = 6 ns

MCM69R736A/818A–7 = 7 ns

MCM69R736A/818A–8 = 8 ns

•

Sleep Mode Operation (ZZ Pin)

119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1

8/20/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69R736A•MCM69R818A

12 3 4 5 6 7...20

中文翻译

下载PDF

与MCM69R736AZP6R相关器件

型号	品牌	获取价格	描述	数据表
MCM69R736AZP7	MOTOROLA	获取价格	4M Late Write HSTL
MCM69R736AZP7R	MOTOROLA	获取价格	4M Late Write HSTL
MCM69R736AZP8	MOTOROLA	获取价格	4M Late Write HSTL
MCM69R736AZP8R	MOTOROLA	获取价格	4M Late Write HSTL
MCM69R736C	FREESCALE	获取价格	4M Late Write HSTL
MCM69R736CZP4	FREESCALE	获取价格	4M Late Write HSTL
MCM69R736CZP4	MOTOROLA	获取价格	128KX36 LATE-WRITE SRAM, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R736CZP4.4	FREESCALE	获取价格	4M Late Write HSTL
MCM69R736CZP4.4	MOTOROLA	获取价格	Late-Write SRAM, 128KX36, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R736CZP4.4R	FREESCALE	获取价格	4M Late Write HSTL

与MCM69R736AZP6R相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

7
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

31

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM69R736AZP6R

MCM69R736AZP6R 数据手册

与MCM69R736AZP6R相关器件

与MCM69R736AZP6R相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM69R736AZP6R

MCM69R736AZP6R 数据手册

与MCM69R736AZP6R相关器件

与MCM69R736AZP6R相关文章

您还可以找

您在本页遇到什么问题？