Datasheet > 存储 > SRAM> MCM69L735ZP7

MCM69L735ZP7

更新时间： 2024-09-19 22:20:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储锁存器静态存储器
页数	文件大小	规格书
16页	186K
描述
128K x 36 Bit Data Latch BurstRAM Synchronous Fast Static RAM

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MCM69L735ZP7 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA,
针数：	119	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	Is Samacsys：	N
Base Number Matches：	1

MCM69L735ZP7 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM69L735

Product Preview

128K x 36 Bit Data Latch

BurstRAM Synchronous

Fast Static RAM

ZP PACKAGE

PBGA

The MCM69L735 is a 4M bit synchronous fast static RAM designed to provide

a burstable, high performance, secondary cache for the PowerPC and other

high performance microprocessors. It is organized as 128K words of 36 bits

each. This device integrates input registers, a 2–bit address counter, and high

speed SRAM onto a single monolithic circuit for reduced parts count in cache

dataRAMapplications. Synchronousdesignallowsprecisecyclecontrolwiththe

use of an external clock (K).

CASE 999–01

Addresses (SA), data inputs (DQx), and all control signals except output

enable(G) and linear burst order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69L735 (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte

writes SBx are asserted with SW. All bytes are written if either SGW is asserted

or if all SBx and SW are asserted.

For read cycles, data is available at the following edge of the clock (K).

The MCM69L735 operates from a 3.3 V core power supply and all outputs

operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

•

MCM69L735 Speed Options

Speed

Setup

0.5 ns

Hold

1 ns

KHKH

KHQV

150 MHz

133 MHz

117 MHz

6.7 ns

7.5 ns

8.5 ns

6 ns

400 mA

375 mA

350 mA

6.5 ns

7 ns

•

3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O

Supply

•

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

PB1 Version 2.0 Compatible

JEDEC Standard 119–Pin PBGA Package

BurstRAM is a trademark of Motorola, Inc.

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

5/28/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69L735

12 3 4 5 6 7...16

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与MCM69L735ZP7相关器件

型号	品牌	获取价格	描述	数据表
MCM69L735ZP7R	MOTOROLA	获取价格	128K x 36 Bit Data Latch BurstRAM Synchronous Fast Static RAM
MCM69L736A	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP10.5	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP10.5R	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP7.5	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP7.5R	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP8.5	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP8.5R	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP9	MOTOROLA	获取价格	128KX36 CACHE SRAM, 9ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69L736AZP9.5	MOTOROLA	获取价格	4M Late Write HSTL

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