Datasheet > 存储 > SRAM> MCM69L736AZP7.5

MCM69L736AZP7.5

更新时间： 2024-11-07 22:06:43

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储静态存储器
页数	文件大小	规格书
20页	228K
描述
4M Late Write HSTL

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中文翻译

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技术参数
数据手册

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MCM69L736AZP7.5 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA,	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.91
Is Samacsys：	N	Base Number Matches：	1

MCM69L736AZP7.5 数据手册

Order this document

by MCM69L736A/D

SEMICONDUCTOR TECHNICAL DATA

MCM69L736A

MCM69L818A

Advance Information

4M Late Write HSTL

The MCM69L736A/818A is a 4M synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM69L818A

(organized as 256K words by 18 bits) and the MCM69L736A (organized as 128K

words by 36 bits) are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK a cycle after address and control

signals. Read data is available at the falling edge of CK.

ZP PACKAGE

PBGA

CASE 999–01

The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V

)

ref

and output voltage (V

) gives the system designer greater flexibility in

DDQ

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable, allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

Single 3.3 V +10%, – 5% Operation

HSTL — I/O (JEDEC Standard JESD8–6 Class I)

HSTL — User Selectable Input Trip–Point

HSTL — Compatible Programmable Impedance Output Drivers

Asynchronous Output Enable

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 Organization

MCM69L736A/818A–7.5 = 7.5 ns

MCM69L736A/818A–8.5 = 8.5 ns

MCM69L736A/818A–9.5 = 9.5 ns

MCM69L736A/818A–10.5 = 10.5 ns

119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

•

This document contains information on a new product. Specifications and information herein are subject to change without notice.

4/3/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69L736A•MCM69L818A

12 3 4 5 6 7...20

中文翻译

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与MCM69L736AZP7.5相关器件

型号	品牌	获取价格	描述	数据表
MCM69L736AZP7.5R	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP8.5	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP8.5R	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP9	MOTOROLA	获取价格	128KX36 CACHE SRAM, 9ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69L736AZP9.5	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736AZP9.5R	MOTOROLA	获取价格	4M Late Write HSTL
MCM69L736CZP5.5	NXP	获取价格	128KX36 LATE-WRITE SRAM, 5.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69L736CZP5.5R	NXP	获取价格	128KX36 LATE-WRITE SRAM, 5.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69L736CZP6.5	NXP	获取价格	128KX36 LATE-WRITE SRAM, 6.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69L736CZP6.5R	NXP	获取价格	128KX36 LATE-WRITE SRAM, 6.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

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