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MCM69D618TQ8R PDF预览

MCM69D618TQ8R

更新时间: 2024-11-09 22:25:39
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器
页数 文件大小 规格书
14页 215K
描述
64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM

MCM69D618TQ8R 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TQFP-100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.91JESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:1179648 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18功能数量:1
端口数量:2端子数量:100
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX18
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

MCM69D618TQ8R 数据手册

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Order this document  
by MCM69D618/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69D618  
64K x 18 Bit Synchronous  
Dual I/O, Dual Address SRAM  
TheMCM69D618isa1M–bitstaticrandomaccessmemory, organizedas64K  
words of 18 bits. It features common data input and data output buffers and  
incorporates input and output registers on–board with high speed SRAM.  
The MCM69D618 allows the user to concurrently perform reads, writes, or  
pass–throughcyclesincombinationonthetwodataports. Thetwoaddressports  
(AX, AY) determine the read or write locations for their respective data ports  
(DQX, DQY).  
TQ PACKAGE  
100 LEAD TQFP  
CASE 983A–01  
The synchronous design allows for precise cycle control with the use of an  
external single clock (K). All signal pins except output enables (GX, GY) are  
registered on the rising edge of clock (K).  
The pass–through feature allows data to be passed from one port to the other,  
in either direction. The PTX input must be asserted to pass data from port X to  
port Y. The PTY will likewise pass data from port Y to port X. A pass–through  
operation takes precedence over a read operation.  
For the case when AX and AY are the same, certain protocols are followed. If  
both ports are read, the reads occur normally. If one port is written and the other  
is read, the read from the array will occur before the data is written. If both ports  
are written, only the data on DQY will be written to the array.  
Single 3.3 V ± 5% Power Supply  
Fast Access Times: 6/8 ns Max  
Throughput of 1.49 Gigabits/Second  
Single Clock Operation  
Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output Registers  
On–Chip  
83 MHz Maximum Clock Frequency  
Self Timed Write  
Two Bi–Directional Data Buses  
Can be Configured as Separate I/O  
Pass–Through Feature  
Asynchronous Output Enables (GX, GY)  
LVTTL Compatible I/O  
Concurrent Reads and Writes  
100–Pin TQFP Package  
Suggested Applications  
— ATM  
— Ethernet Switches — Routers  
— Cell/Frame Buffers — SNA Switches  
— Shared Memory  
Product Family Configurations  
Part  
Number  
Dual  
Address  
Single  
Address  
Dual  
I/O  
Separate  
I/O  
Configuration  
32K x 36  
V
DD  
MCM69D536  
MCM69D618  
MCM67Q709A  
MCM67Q909  
NOTES:  
Note 1  
Note 1  
Note 2  
Note 2  
3.3 V  
3.3 V  
5.0 V  
5.0 V  
64K x 18  
128K x 9  
512K x 9  
1. Tie AX and AY address ports together for the part to function as a single address part.  
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.  
REV 5  
1/16/98  
Motorola, Inc. 1998  

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