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MCM69C433TQ20 PDF预览

MCM69C433TQ20

更新时间: 2024-09-19 20:54:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
21页 259K
描述
16KX64 CONTENT ADDRESSABLE SRAM, 240ns, PQFP100, TQFP-100

MCM69C433TQ20 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP100,.63X.87针数:100
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.8
最长访问时间:240 nsJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:1048576 bit内存集成电路类型:CONTENT ADDRESSABLE SRAM
内存宽度:64功能数量:1
端子数量:100字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX64封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.3 A
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):3.5 V最小供电电压 (Vsup):3.1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

MCM69C433TQ20 数据手册

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Order this document  
by MCM69C433/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69C433  
Advance Information  
16K x 64 CAM  
The MCM69C433 is a flexible content–addressable memory (CAM) that can  
contain 16K entries of 64 bits each. The widths of the match field and the output  
field are programmable, and the match time is designed to be 240 ns. As a result,  
the MCM69C433 is well suited for datacom applications such as Virtual Path  
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to  
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup  
in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C433 is  
user–defined, with a trade–off between the time between matches and the rate  
of new entries added to the CAM per second.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
16K Entries  
240 ns Match Time  
Mask Register to “Don’t Care” Selected Bits  
Depth Expansion by Cascading Multiple Devices  
66 MHz Maximum Clock Rate  
Programmable Match and Output Field Widths  
Concurrent Matching of Virtual Path Circuits and Virtual Connection  
Circuits in ATM Mode  
Separate Ports for Control and Match Operations  
450 ns Insertion Time if 1 of 14 Entry Queue Locations is Empty  
120 ms Initialization Time After Fast Insertion (at Power–Up Only)  
Single 3.3 V ±5% Supply  
IEEE Standard 1149.1 Test Port (JTAG)  
100–Pin TQFP Package  
Related Products  
— MCM69D536, MCM69D618 (Dual I/O, Dual Address RAMs)  
— MCM67Q709A, MCM67Q909 (Separate I/O RAMs)  
— MCM69C232, MCM69C432, MCM69C233 (CAMs)  
CONTROL PORT  
MATCH PORT  
14 x 64  
ENTRY QUEUE  
MQ31 – MQ0  
A2 – A0  
DQ15 – DQ0  
STATUS/  
CONTROL  
LOGIC  
16K x 64  
CAM  
TABLE  
K
SEL  
G
WE  
IRQ  
LH/SM  
LL  
DTACK  
MC  
MS  
INPUT REG  
RESET  
KMODE  
VPC  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
10/15/99  
Motorola, Inc. 1999  

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