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MCM69D536TQ8 PDF预览

MCM69D536TQ8

更新时间: 2024-09-18 22:20:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 静态存储器
页数 文件大小 规格书
14页 216K
描述
32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM

MCM69D536TQ8 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:176
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.55
最长访问时间:8 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:S-PQFP-G176JESD-609代码:e0
长度:24 mm内存密度:1179648 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:36
功能数量:1端子数量:176
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX36
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:24 mm
Base Number Matches:1

MCM69D536TQ8 数据手册

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Order this document  
by MCM69D536/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69D536  
32K x 36 Bit Synchronous  
Dual I/O, Dual Address SRAM  
TheMCM69D536isa1M–bitstaticrandomaccessmemory, organizedas32K  
words of 36 bits. It features common data input and data output buffers and  
incorporates input and output registers on–board with high speed SRAM.  
The MCM69D536 allows the user to concurrently perform reads, writes, or  
pass–throughcyclesincombinationonthetwodataports. Thetwoaddressports  
(AX, AY) determine the read or write locations for their respective data ports  
(DQX, DQY).  
The synchronous design allows for precise cycle control with the use of an  
external single clock (K). All signal pins except output enables (GX, GY) are  
registered on the rising edge of clock (K).  
TQ PACKAGE  
176 LEAD TQFP  
CASE 1101–01  
The pass–through feature allows data to be passed from one port to the other,  
in either direction. The PTX input must be asserted to pass data from port X to  
port Y. The PTY will likewise pass data from port Y to port X. A pass–through  
operation takes precedence over a read operation.  
For the case when AX and AY are the same, certain protocols are followed. If  
both ports are read, the reads occur normally. If one port is written and the other  
is read, the read from the array will occur before the data is written. If both ports  
are written, only the data on DQY will be written to the array.  
Single 3.3 V ± 5% Power Supply  
Fast Access Times: 6/8 ns Max  
Throughput of 2.98 Gigabits/Second  
Single Clock Operation  
Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output  
Registers On–Chip  
83 MHz Maximum Clock Frequency  
Self–Timed Write  
Two Bi–Directional Data Buses  
Can be Configured as Separate I/O  
Pass–Through Feature  
Asynchronous Output Enables (GX, GY)  
LVTTL Compatible I/O  
Concurrent Reads and Writes  
176–Pin TQFP Package  
Suggested Applications  
— ATM  
— Ethernet Switches — Routers  
— Cell/Frame Buffers — SNA Switches  
— Shared Memory  
Product Family Configurations  
Part  
Number  
Dual  
Address  
Single  
Address  
Dual  
I/O  
Separate  
I/O  
Configuration  
32K x 36  
V
DD  
MCM69D536  
MCM69D618  
MCM67Q709A  
Note 1  
Note 1  
Note 2  
Note 2  
3.3 V  
3.3 V  
5.0 V  
5.0 V  
64K x 18  
128K x 9  
MCM67Q909  
NOTES:  
512K x 9  
1. Tie AX and AY address ports together for the part to function as a single address part.  
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.  
REV 4  
1/16/98  
Motorola, Inc. 1998  

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