Datasheet > MCM69D536

MCM69D536

更新时间： 2024-11-09 22:20:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器
页数	文件大小	规格书
14页	216K
描述
32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM

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MCM69D536 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM69D536

32K x 36 Bit Synchronous

Dual I/O, Dual Address SRAM

TheMCM69D536isa1M–bitstaticrandomaccessmemory, organizedas32K

words of 36 bits. It features common data input and data output buffers and

incorporates input and output registers on–board with high speed SRAM.

The MCM69D536 allows the user to concurrently perform reads, writes, or

pass–throughcyclesincombinationonthetwodataports. Thetwoaddressports

(AX, AY) determine the read or write locations for their respective data ports

(DQX, DQY).

The synchronous design allows for precise cycle control with the use of an

external single clock (K). All signal pins except output enables (GX, GY) are

registered on the rising edge of clock (K).

TQ PACKAGE

176 LEAD TQFP

CASE 1101–01

The pass–through feature allows data to be passed from one port to the other,

in either direction. The PTX input must be asserted to pass data from port X to

port Y. The PTY will likewise pass data from port Y to port X. A pass–through

operation takes precedence over a read operation.

For the case when AX and AY are the same, certain protocols are followed. If

both ports are read, the reads occur normally. If one port is written and the other

is read, the read from the array will occur before the data is written. If both ports

are written, only the data on DQY will be written to the array.

•

Single 3.3 V ± 5% Power Supply

Fast Access Times: 6/8 ns Max

Throughput of 2.98 Gigabits/Second

Single Clock Operation

Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output

Registers On–Chip

•

83 MHz Maximum Clock Frequency

Self–Timed Write

Two Bi–Directional Data Buses

Can be Configured as Separate I/O

Pass–Through Feature

Asynchronous Output Enables (GX, GY)

LVTTL Compatible I/O

Concurrent Reads and Writes

176–Pin TQFP Package

Suggested Applications

— ATM

— Ethernet Switches — Routers

— Cell/Frame Buffers — SNA Switches

— Shared Memory

Product Family Configurations

Part

Number

Dual

Address

Single

Address

Dual

I/O

Separate

I/O

Configuration

32K x 36

MCM69D536

MCM69D618

MCM67Q709A

Note 1

Note 2

3.3 V

5.0 V

64K x 18

128K x 9

MCM67Q909

NOTES:

512K x 9

1. Tie AX and AY address ports together for the part to function as a single address part.

2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.

REV 4

1/16/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69D536

12 3 4 5 6 7...14

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与MCM69D536相关器件

型号	品牌	获取价格	描述	数据表
MCM69D536TQ10	MOTOROLA	获取价格	32KX36 MULTI-PORT SRAM, PQFP176, TQFP-176
MCM69D536TQ10R	MOTOROLA	获取价格	32KX36 MULTI-PORT SRAM, PQFP176, TQFP-176
MCM69D536TQ5	MOTOROLA	获取价格	32KX36 DUAL-PORT SRAM, 5ns, PQFP176, TQFP-176
MCM69D536TQ5R	MOTOROLA	获取价格	Dual-Port SRAM, 32KX36, 5ns, CMOS, PQFP176, TQFP-176
MCM69D536TQ6	MOTOROLA	获取价格	32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM
MCM69D536TQ6R	MOTOROLA	获取价格	32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM
MCM69D536TQ8	MOTOROLA	获取价格	32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM
MCM69D536TQ8R	MOTOROLA	获取价格	32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM
MCM69D618	MOTOROLA	获取价格	64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM
MCM69D618TQ10	MOTOROLA	获取价格	Standard SRAM, 64KX18, 10ns, MOS, PQFP100, TQFP-100

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