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MC74VHC595M

更新时间： 2024-11-20 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 移位寄存器存储触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 210K
描述
8-Bit Shift Register with Output Storage Register

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中文翻译

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MC74VHC595M 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：EIAJ, SOIC-16
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.43
Is Samacsys：N其他特性：SISO OPERATION ALSO AVAILABLE
计数方向：RIGHT系列：AHC/VHC
JESD-30 代码：R-PDSO-G16JESD-609代码：e0
长度：10.2 mm逻辑集成电路类型：SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup：50000000 Hz位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/5.5 V传播延迟（tpd）：17 ns
认证状态：Not Qualified座面最大高度：2.05 mm
子类别：Shift Registers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：5.275 mm
最小 fmax：115 MHzBase Number Matches：1

MC74VHC595M 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC595 is an advanced high speed 8–bit shift register with an  
output storage register fabricated with silicon gate CMOS technology.  
It achieves high speed operation similar to equivalent Bipolar Schottky  
TTL while maintaining CMOS low power dissipation.  
The MC74VHC595 contains an 8–bit static shift register which feeds an  
8–bit storage register.  
D SUFFIX  
16–LEAD SOIC PACKAGE  
CASE 751B–05  
Shift operation is accomplished on the positive going transition of the Shift  
Clock input (SCK). The output register is loaded with the contents of the shift  
register on the positive going transition of the Register Clock input (RCK).  
Since the RCK and SCK signals are independent, parallel outputs can be  
held stable during the shift operation. And, since the parallel outputs are  
3–state, the VHC595 can be directly connected to an 8–bit bus. This register  
can be used in serial–to–parallel conversion, data receivers, etc.  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
DT SUFFIX  
16–LEAD TSSOP PACKAGE  
CASE 948F–01  
M SUFFIX  
16–LEAD SOIC EIAJ PACKAGE  
CASE 966–01  
•
•
•
•
•
•
•
•
•
•
•
High Speed: f  
= 185MHz (Typ) at V  
= 5V  
max  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIL CC  
NIH  
ORDERING INFORMATION  
MC74VHCXXXD  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC  
TSSOP  
SOIC EIAJ  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 1.0V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 328 FETs or 82 Equivalent Gates  
PIN ASSIGNMENT  
QB  
QC  
1
2
16  
15  
VCC  
QA  
QD  
QE  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
SI  
LOGIC DIAGRAM  
OE  
SERIAL  
DATA  
INPUT  
QF  
RCK  
SCK  
SCLR  
SQH  
14  
15  
1
SI  
QA  
QB  
QG  
QH  
2
3
4
5
QC  
GND  
PARALLEL  
DATA  
OUTPUTS  
QD  
QE  
QF  
QG  
QH  
SHIFT  
STORAGE  
REGISTER  
REGISTER  
6
7
11  
10  
12  
13  
SCK  
SERIAL  
DATA  
OUTPUT  
9
SQH  
SCLR  
RCK  
OE  
6/97  
REV 1  
Motorola, Inc. 1997  
1234567...9

中文翻译

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