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MC74VHC86D PDF预览

MC74VHC86D

更新时间: 2024-11-05 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路石英晶振光电二极管
页数 文件大小 规格书
5页 140K
描述
Quad 2-Input XOR Gate

MC74VHC86D 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC86 is an advanced high speed CMOS 2–input Exclu-  
sive–OR gate fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
D SUFFIX  
14–LEAD SOIC PACKAGE  
CASE 751A–03  
High Speed: t  
= 4.8ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIH  
NIL CC  
DT SUFFIX  
14–LEAD TSSOP PACKAGE  
CASE 948G–01  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 56 FETs or 14 Equivalent Gates  
M SUFFIX  
14–LEAD SOIC EIAJ PACKAGE  
CASE 965–01  
LOGIC DIAGRAM  
1
ORDERING INFORMATION  
A1  
3
Y1  
Y2  
Y3  
Y4  
2
4
MC74VHCXXD  
MC74VHCXXDT  
MC74VHCXXM  
SOIC  
TSSOP  
SOICEIAJ  
B1  
A2  
6
8
5
9
B2  
A3  
Y = A  
B
FUNCTION TABLE  
10  
12  
B3  
A4  
Inputs  
Output  
Y
11  
13  
A
B
B4  
L
L
L
H
L
L
H
H
L
H
H
H
Pinout: 14–Lead Packages (Top View)  
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
14  
1
2
3
4
5
6
7
A1  
B1  
Y1  
A2  
B2  
Y2  
GND  
6/97  
REV 0  
Motorola, Inc. 1997  

MC74VHC86D 替代型号

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MM74HC86M ONSEMI

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