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MC74VHC74DTRG

更新时间： 2024-11-21 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
6页 159K
描述
AHC/VHC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, LEAD FREE, TSSOP-14

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MC74VHC74DTRG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.62系列：AHC/VHC
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：5 mm逻辑集成电路类型：D FLIP-FLOP
位数：1功能数量：2
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：17.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：110 MHz
Base Number Matches：1

MC74VHC74DTRG 数据手册

 浏览型号MC74VHC74DTRG的Datasheet PDF文件第2页浏览型号MC74VHC74DTRG的Datasheet PDF文件第3页浏览型号MC74VHC74DTRG的Datasheet PDF文件第4页浏览型号MC74VHC74DTRG的Datasheet PDF文件第5页浏览型号MC74VHC74DTRG的Datasheet PDF文件第6页 
MC74VHC74  
Dual D−Type Flip−Flop  
with Set and Reset  
The MC74VHC74 is an advanced high speed CMOS D−type  
flip−flop fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
The signal level applied to the D input is transferred to Q output  
during the positive going transition of the Clock pulse.  
Reset (RD) and Set (SD) are independent of the Clock (CP) and are  
accomplished by setting the appropriate input Low.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
1
SOIC−14  
D SUFFIX  
CASE 751A  
VHC74G  
AWLYWW  
1
14  
Features  
VHC  
74  
TSSOP−14  
DT SUFFIX  
CASE 948G  
• High Speed: f  
• Low Power Dissipation: I = 2mA (Max) at T = 25°C  
• High Noise Immunity: V  
= 170MHz (Typ) at V = 5V  
CC  
max  
ALYWG  
CC  
A
1
G
= V = 28% V  
NIL CC  
NIH  
1
• Power Down Protection Provided on Inputs  
• Balanced Propagation Delays  
14  
• Designed for 2.0 V to 5.5 V Operating Range  
SOEIAJ−14  
M SUFFIX  
CASE 965  
VHC74  
ALYWG  
• Low Noise: V  
= 0.8 V (Max)  
OLP  
1
• Pin and Function Compatible with Other Standard Logic Families  
• Latchup Performance Exceeds 300 mA  
1
• ESD Performance:  
A
= Assembly Location  
Human Body Model > 2000 V;  
Machine Model > 200 V  
WL, L = Wafer Lot  
Y, YY = Year  
• Chip Complexity: 128 FETs or 32 Equivalent Gates  
• Pb−Free Packages are Available*  
WW, W = Work Week  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
13  
12  
11  
10  
1
2
3
4
FUNCTION TABLE  
RD1  
D1  
RD2  
D2  
Inputs  
Outputs  
9
8
5
6
Q2  
Q2  
Q1  
Q1  
SD  
RD  
CP  
D
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*  
H
L
L
H
H*  
L
CP1  
SD1  
CP2  
SD2  
H
L
H
No Change  
No Change  
No Change  
Figure 1. LOGIC DIAGRAM  
*Both outputs will remain high as long as Set and Re-  
set are low, but the output states are unpredictable  
if Set and Reset go high simultaneously.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
March, 2006 − Rev. 5  
MC74VHC74/D  
123456

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