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MC74VHC74M PDF预览

MC74VHC74M

更新时间: 2024-11-20 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 157K
描述
Dual D-Type Flip-Flop with Set and Reset

MC74VHC74M 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.08Is Samacsys:N
系列:AHC/VHCJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:75000000 Hz最大I(ol):0.008 A
位数:1功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:2/5.5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):10.5 ns
认证状态:Not Qualified座面最大高度:2.05 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:5.275 mm最小 fmax:75 MHz
Base Number Matches:1

MC74VHC74M 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC74 is an advanced high speed CMOS D–type flip–flop  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
The signal level applied to the D input is transferred to Q output during the  
positive going transition of the Clock pulse.  
D SUFFIX  
14–LEAD SOIC PACKAGE  
CASE 751A–03  
Reset (RD) and Set (SD) are independent of the Clock (CP) and are  
accomplished by setting the appropriate input Low.  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
DT SUFFIX  
14–LEAD TSSOP PACKAGE  
CASE 948G–01  
High Speed: f  
= 170MHz (Typ) at V  
= 5V  
max  
Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
CC  
NIH  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIL CC  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8V (Max)  
M SUFFIX  
14–LEAD SOIC EIAJ PACKAGE  
CASE 965–01  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 128 FETs or 32 Equivalent Gates  
ORDERING INFORMATION  
MC74VHCXXD  
MC74VHCXXDT  
MC74VHCXXM  
SOIC  
TSSOP  
SOICEIAJ  
LOGIC DIAGRAM  
13  
12  
11  
10  
1
2
3
4
RD1  
D1  
RD2  
D2  
PIN ASSIGNMENT  
9
8
5
6
Q2  
Q2  
Q1  
Q1  
RD1  
D1  
1
2
14  
13  
V
CC  
CP1  
SD1  
CP2  
SD2  
RD2  
3
4
12  
11  
CP1  
SD1  
D2  
CP2  
Q1  
Q1  
5
6
10  
9
SD2  
Q2  
GND  
7
8
Q2  
FUNCTION TABLE  
Inputs  
Outputs  
SD  
RD  
CP  
D
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*  
H
L
L
H
H*  
L
H
L
H
No Change  
No Change  
No Change  
* Both outputs will remain high as long as Set and Reset are low, but the output  
states are unpredictable if Set and Reset go high simultaneously.  
6/97  
REV 1  
Motorola, Inc. 1997  

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