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MC74VHC74DR2 PDF预览

MC74VHC74DR2

更新时间: 2024-11-06 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
6页 159K
描述
Dual D−Type Flip−Flop with Set and Reset

MC74VHC74DR2 数据手册

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MC74VHC74  
Dual D−Type Flip−Flop  
with Set and Reset  
The MC74VHC74 is an advanced high speed CMOS Dtype  
flipflop fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
The signal level applied to the D input is transferred to Q output  
during the positive going transition of the Clock pulse.  
Reset (RD) and Set (SD) are independent of the Clock (CP) and are  
accomplished by setting the appropriate input Low.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
1
SOIC14  
D SUFFIX  
CASE 751A  
VHC74G  
AWLYWW  
1
14  
Features  
VHC  
74  
TSSOP14  
DT SUFFIX  
CASE 948G  
High Speed: f  
Low Power Dissipation: I = 2mA (Max) at T = 25°C  
High Noise Immunity: V  
= 170MHz (Typ) at V = 5V  
CC  
max  
ALYWG  
CC  
A
1
G
= V = 28% V  
NIL CC  
NIH  
1
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
14  
Designed for 2.0 V to 5.5 V Operating Range  
SOEIAJ14  
M SUFFIX  
CASE 965  
VHC74  
ALYWG  
Low Noise: V  
= 0.8 V (Max)  
OLP  
1
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
1
ESD Performance:  
A
= Assembly Location  
Human Body Model > 2000 V;  
Machine Model > 200 V  
WL, L = Wafer Lot  
Y, YY = Year  
Chip Complexity: 128 FETs or 32 Equivalent Gates  
PbFree Packages are Available*  
WW, W = Work Week  
G or G = PbFree Package  
(Note: Microdot may be in either location)  
13  
12  
11  
10  
1
2
3
4
FUNCTION TABLE  
RD1  
D1  
RD2  
D2  
Inputs  
Outputs  
9
8
5
6
Q2  
Q2  
Q1  
Q1  
SD  
RD  
CP  
D
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*  
H
L
L
H
H*  
L
CP1  
SD1  
CP2  
SD2  
H
L
H
No Change  
No Change  
No Change  
Figure 1. LOGIC DIAGRAM  
*Both outputs will remain high as long as Set and Re-  
set are low, but the output states are unpredictable  
if Set and Reset go high simultaneously.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
March, 2006 Rev. 5  
MC74VHC74/D  

MC74VHC74DR2 替代型号

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