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MC14094B_05

更新时间： 2024-11-04 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI 存储
页数 文件大小 规格书
10页 121K
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8−Stage Shift/Store Register with Three−State Outputs

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MC14094B_05 数据手册

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MC14094B  
8−Stage Shift/Store Register  
with Three−State Outputs  
The MC14094B combines an 8−stage shift register with a data latch  
for each stage and a 3−state output from each latch.  
Data is shifted on the positive clock transition and is shifted from the  
http://onsemi.com  
MARKING  
seventh stage to two serial outputs. The Q output data is for use in  
S
high−speed cascaded systems. The Q output data is shifted on the  
S
following negative clock transition for use in low−speed cascaded  
systems.  
DIAGRAMS  
Data from each stage of the shift register is latched on the negative  
transition of the strobe input. Data propagates through the latch while  
strobe is high.  
Outputs of the eight data latches are controlled by 3−state buffers  
which are placed in the high−impedance state by a logic Low on  
Output Enable.  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC14094BCP  
AWLYYWWG  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14094BG  
AWLYWW  
Features  
• 3−State Outputs  
1
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
• Input Diode Protection  
16  
14  
094B  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
• Data Latch  
• Dual Outputs for Data Out on Both Positive and  
Negative Clock Transitions  
1
• Useful for Serial−to−Parallel Data Conversion  
• Pin−for−Pin Compatible with CD4094B  
• Pb−Free Packages are Available*  
16  
1
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC14094B  
ALYWG  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
V
DC Supply Voltage Range  
DD  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
V , V  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
in out  
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
± 10  
mA  
WW, W = Work Week  
G
= Pb−Free Indicator  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
T
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
A
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14094B/D  
 
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