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MC14094BDTR2G PDF预览

MC14094BDTR2G

更新时间: 2024-11-23 12:06:03
品牌 Logo 应用领域
安森美 - ONSEMI 存储
页数 文件大小 规格书
10页 161K
描述
8-Stage Shift/Store Register with Three-State Outputs

MC14094BDTR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:0.97计数方向:RIGHT
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
逻辑集成电路类型:SERIAL IN PARALLEL OUT最大频率@ Nom-Sup:1250000 Hz
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5/15 V传播延迟(tpd):840 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Shift Registers标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:3 MHzBase Number Matches:1

MC14094BDTR2G 数据手册

 浏览型号MC14094BDTR2G的Datasheet PDF文件第2页浏览型号MC14094BDTR2G的Datasheet PDF文件第3页浏览型号MC14094BDTR2G的Datasheet PDF文件第4页浏览型号MC14094BDTR2G的Datasheet PDF文件第5页浏览型号MC14094BDTR2G的Datasheet PDF文件第6页浏览型号MC14094BDTR2G的Datasheet PDF文件第7页 
MC14094B  
8-Stage Shift/Store Register  
with Three-State Outputs  
The MC14094B combines an 8stage shift register with a data latch  
for each stage and a 3state output from each latch.  
Data is shifted on the positive clock transition and is shifted from the  
http://onsemi.com  
MARKING DIAGRAMS  
seventh stage to two serial outputs. The Q output data is for use in  
S
highspeed cascaded systems. The Q output data is shifted on the  
S
following negative clock transition for use in lowspeed cascaded systems.  
Data from each stage of the shift register is latched on the negative  
transition of the strobe input. Data propagates through the latch while  
strobe is high.  
Outputs of the eight data latches are controlled by 3state buffers which  
are placed in the highimpedance state by a logic Low on Output Enable.  
16  
PDIP16  
P SUFFIX  
CASE 648  
MC14094BCP  
AWLYYWWG  
1
16  
SOIC16  
D SUFFIX  
CASE 751B  
14094BG  
AWLYWW  
Features  
3State Outputs  
1
Capable of Driving Two LowPower TTL Loads or One LowPower  
Schottky TTL Load Over the Rated Temperature Range  
Input Diode Protection  
16  
14  
094B  
ALYWG  
G
TSSOP16  
DT SUFFIX  
CASE 948F  
Data Latch  
1
16  
Dual Outputs for Data Out on Both Positive and  
Negative Clock Transitions  
SOEIAJ16  
F SUFFIX  
CASE 966  
Useful for SerialtoParallel Data Conversion  
MC14094B  
ALYWG  
PinforPin Compatible with CD4094B  
These Devices are PbFree and are RoHS Compliant  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
1
A
= Assembly Location  
= Wafer Lot  
= Year  
WL, L  
YY, Y  
WW, W = Work Week  
G or G  
= PbFree Indicator  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
Unit  
V
V
DD  
DC Supply Voltage Range  
0.5 to +18.0  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
P
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
500  
mW  
°C  
D
T
A
55 to +125  
65 to +150  
260  
T
stg  
Storage Temperature Range  
°C  
T
Lead Temperature  
°C  
L
(8Second Soldering)  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be  
taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V and V  
in  
out  
should be constrained to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
May, 2013 Rev. 9  
MC14094B/D  
 

MC14094BDTR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC14094BDTR2 ONSEMI

完全替代

8-Stage Shift/Store Register with Three-State Outputs
CD4094BPWRG4 TI

类似代替

CMOS 8-Stage Shift-and-Store Nus Register
CD4094BPWR TI

类似代替

CMOS 8-Stage Shift-and-Store Nus Register

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