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MC14099B_05

更新时间： 2024-11-04 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
8页 101K
描述
8−Bit Addressable Latches

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MC14099B_05 数据手册

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MC14099B  
8−Bit Addressable Latches  
The MC14099B is an 8−bit addressable latch. Data is entered in  
serial form when the appropriate latch is addressed (via address pins  
A0, A1, A2) and write disable is in the low state. For the MC14099B  
the input is a unidirectional write only port.  
The data is presented in parallel at the output of the eight latches  
independently of the state of Write Disable, Write/Read or Chip  
Enable.  
http://onsemi.com  
MARKING  
A Master Reset capability is available on both parts.  
DIAGRAMS  
Features  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC14099BCP  
AWLYYWWG  
• Serial Data Input  
• Parallel Output  
• Master Reset  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
16  
• Capable of Driving Two Low−power TTL Loads or One Low−Power  
Schottky TTL Load over the Rated Temperature Range  
• MC14099B pin for pin compatible with CD4099B  
• Pb−Free Packages are Available*  
SOIC−16  
DW SUFFIX  
CASE 751G  
14099BG  
AWLYYWW  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
16  
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC14099B  
ALYWG  
V
DC Supply Voltage Range  
DD  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
1
I , I  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
in out  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
WW, W = Work Week  
G
= Pb−Free Indicator  
T
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
L
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14099B/D  
 
12345678

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