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MC14099BCP

更新时间： 2024-11-05 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
9页 290K
描述
8-Bit Addressable Latches

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中文翻译

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MC14099BCP 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：PLASTIC, DIP-16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.7
其他特性：1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH系列：4000/14000/40000
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
长度：19.175 mm负载电容（CL）：50 pF
逻辑集成电路类型：D LATCH最大I（ol）：0.0042 A
位数：1功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5/15 V
Prop。Delay @ Nom-Sup：400 ns传播延迟（tpd）：400 ns
认证状态：Not Qualified座面最大高度：4.44 mm
子类别：FF/Latches最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：LOW LEVEL
宽度：7.62 mmBase Number Matches：1

MC14099BCP 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC14099B and MC14599B are 8–bit addressable latches. Data is  
entered in serial form when the appropriate latch is addressed (via address  
pins A0, A1, A2) and write disable is in the low state. Chip enable must be  
high for writing into MC14599B. For the MC14599B the data pin is a  
bidirectional data port and for the MC14099B the input is a unidirectional  
write only port. The Write/Read line controls this port in the MC14599B.  
The data is presented in parallel at the output of the eight latches  
independently of the state of Write Disable, Write/Read or Chip Enable.  
A Master Reset capability is available on both parts.  
L SUFFIX  
CERAMIC  
CASE 620  
P SUFFIX  
PLASTIC  
CASE 648  
•
•
•
•
•
Serial Data Input  
Parallel Output  
Master Reset  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–Power  
Schottky TTL Load over the Rated Temperature Range  
MC14099B pin for pin compatible with CD4099B  
DW SUFFIX  
SOIC  
CASE 751G  
•
ORDERING INFORMATION  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
MC14099BCP  
MC14099BCL  
MC14099BDW  
Plastic  
Ceramic  
SOIC  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
– 0.5 to + 18.0  
DD  
V , V  
T
A
= – 55° to 125°C for all packages.  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
L SUFFIX  
CERAMIC  
CASE 726  
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
P SUFFIX  
PLASTIC  
CASE 707  
MC14099B  
MC14599B  
8
CHIP ENABLE  
WRITE/READ  
WRITE DISABLE  
10  
4
3
11  
12  
13  
14  
15  
16  
17  
1
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
9
4
3
ORDERING INFORMATION  
WRITE DISABLE  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
DATA  
10  
11  
12  
13  
14  
15  
1
DATA  
8
MC14599BCP  
MC14599BCL  
Plastic  
Ceramic  
5
6
7
8
5
6
7
A0  
A1  
A2  
LATCHES  
8
A0  
A1  
A2  
8
DECODER  
LATCHES  
DECODER  
T
A
= – 55° to 125°C for all packages.  
2
RESET  
2
RESET  
V
= 18  
= 9  
DD  
V
= 16  
= 8  
DD  
V
SS  
V
SS  
PIN ASSIGNMENT  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
Q7  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
V
DD  
PIN ASSIGNMENT  
Q7  
1
2
16  
15  
V
RESET  
Q6  
Q5  
Q4  
Q3  
Q2  
Q1  
Q0  
DD  
RESET  
Q6  
Q5  
Q4  
Q3  
Q2  
Q1  
Q0  
DATA  
WRITE  
DISABLE  
DATA  
WRITE  
DISABLE  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
operation, V and V  
should be constrained  
in out  
to the range V  
(V or V  
)
V
DD  
.
SS in out  
A0  
A1  
A2  
CE  
Unused inputs must always be tied to an  
appropriate logic voltage level (e.g., either V  
A0  
A1  
A2  
SS  
or V ). Unused outputs must be left open.  
DD  
WRITE/  
READ  
V
V
SS  
SS  
REV 0  
1/94  
Motorola, Inc. 1995  
1234567...9

中文翻译

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