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MC14094BDR2G PDF预览

MC14094BDR2G

更新时间： 2024-11-19 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI 移位寄存器存储触发器逻辑集成电路光电二极管PC
页数 文件大小 规格书
10页 121K
描述
8−Stage Shift/Store Register with Three−State Outputs

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中文翻译

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MC14094BDR2G 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：LEAD FREE, PLASTIC, SOIC-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：0.89
Samacsys Confidence：2Samacsys Status：Released
Samacsys PartID：411610Samacsys Pin Count：16
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：SOIC-16 CASE751B-05Samacsys Released Date：2017-05-04 08:31:21
Is Samacsys：N计数方向：RIGHT
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：9.9 mm
逻辑集成电路类型：SERIAL IN PARALLEL OUT最大频率@ Nom-Sup：1250000 Hz
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5/15 V传播延迟（tpd）：840 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Shift Registers标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：3 MHzBase Number Matches：1

MC14094BDR2G 数据手册

 浏览型号MC14094BDR2G的Datasheet PDF文件第2页浏览型号MC14094BDR2G的Datasheet PDF文件第3页浏览型号MC14094BDR2G的Datasheet PDF文件第4页浏览型号MC14094BDR2G的Datasheet PDF文件第5页浏览型号MC14094BDR2G的Datasheet PDF文件第6页浏览型号MC14094BDR2G的Datasheet PDF文件第7页 
MC14094B  
8−Stage Shift/Store Register  
with Three−State Outputs  
The MC14094B combines an 8−stage shift register with a data latch  
for each stage and a 3−state output from each latch.  
Data is shifted on the positive clock transition and is shifted from the  
http://onsemi.com  
MARKING  
seventh stage to two serial outputs. The Q output data is for use in  
S
high−speed cascaded systems. The Q output data is shifted on the  
S
following negative clock transition for use in low−speed cascaded  
systems.  
DIAGRAMS  
Data from each stage of the shift register is latched on the negative  
transition of the strobe input. Data propagates through the latch while  
strobe is high.  
Outputs of the eight data latches are controlled by 3−state buffers  
which are placed in the high−impedance state by a logic Low on  
Output Enable.  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC14094BCP  
AWLYYWWG  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14094BG  
AWLYWW  
Features  
• 3−State Outputs  
1
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
• Input Diode Protection  
16  
14  
094B  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
• Data Latch  
• Dual Outputs for Data Out on Both Positive and  
Negative Clock Transitions  
1
• Useful for Serial−to−Parallel Data Conversion  
• Pin−for−Pin Compatible with CD4094B  
• Pb−Free Packages are Available*  
16  
1
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC14094B  
ALYWG  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
V
DC Supply Voltage Range  
DD  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
V , V  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
in out  
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
± 10  
mA  
WW, W = Work Week  
G
= Pb−Free Indicator  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
T
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
A
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14094B/D  
 
1234567...10

中文翻译

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MC14094BDR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC14094BFG ONSEMI

完全替代

 8−Stage Shift/Store Register with Three−State Outputs
MC14094BFELG ONSEMI

完全替代

 8−Stage Shift/Store Register with Three−State Outputs
MC14094BD ONSEMI

完全替代

 8-Stage Shift/Store Register with Three-State Outputs

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MC14094BFELG ONSEMI

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