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MC14094BCPD

更新时间： 2024-11-23 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器存储触发器逻辑集成电路输出元件
页数 文件大小 规格书
6页 235K
描述
4000/14000/40000 SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, 648-08

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MC14094BCPD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.58
其他特性：PARALLEL OUTPUT IS LATCHED; UNLATCHED SERIAL SHIFT RIGHT OUTPUT计数方向：RIGHT
系列：4000/14000/40000JESD-30 代码：R-PDIP-T16
JESD-609代码：e0长度：19.175 mm
负载电容（CL）：50 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
位数：8功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
传播延迟（tpd）：840 ns认证状态：Not Qualified
座面最大高度：4.44 mm子类别：Shift Registers
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：1.25 MHz
Base Number Matches：1

MC14094BCPD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14094B combines an 8–stage shift register with a data latch for  
each stage and a three–state output from each latch.  
Data is shifted on the positive clock transition and is shifted from the  
seventh stage to two serial outputs. The Q output data is for use in  
S
P SUFFIX  
PLASTIC  
CASE 648  
high–speed cascaded systems. The Q′ output data is shifted on the  
S
following negative clock transition for use in low–speed cascaded systems.  
Data from each stage of the shift register is latched on the negative  
transition of the strobe input. Data propagates through the latch while strobe  
is high.  
D SUFFIX  
SOIC  
CASE 751B  
Outputs of the eight data latches are controlled by three–state buffers  
which are placed in the high–impedance state by a logic Low on Output  
Enable.  
•
•
Three–State Outputs  
ORDERING INFORMATION  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
Input Diode Protection  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
•
•
•
Data Latch  
T
= – 55° to 125°C for all packages.  
A
Dual Outputs for Data Out on Both Positive and Negative Clock  
Transitions  
•
•
Useful for Serial–to–Parallel Data Conversion  
Pin–for–Pin Compatible with CD4094B  
PIN ASSIGNMENT  
STROBE  
1
2
16  
15  
V
DD  
OUTPUT  
ENABLE  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
DATA  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
CLOCK  
Q1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
Q5  
Q6  
Q7  
Q8  
V
– 0.5 to + 18.0  
DD  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
Q2  
I , I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
Q3  
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
Q4  
Q′  
S
T
stg  
– 65 to + 150  
260  
V
Q
SS  
S
T
L
Lead Temperature (8–Second Soldering)  
C
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
Parallel Outputs  
Serial Outputs  
Output  
Enable  
Clock  
Strobe  
Data  
Q1  
Z
Q
Q *  
S
Q′  
S
N
operation, V and V  
should be constrained  
in  
out  
0
0
1
1
1
1
X
X
0
1
1
1
X
X
X
0
1
1
Z
Q7  
No Chg.  
Q7  
No Chg.  
Q7  
to the range V  
(V or V  
)
V
DD  
.
SS  
in out  
Z
Z
Unused inputs must always be tied to an  
appropriate logic voltage level (e.g., either V  
SS  
or V ). Unused outputs must be left open.  
No Chg. No Chg.  
No Chg.  
No Chg.  
No Chg.  
Q7  
DD  
0
1
Q –1  
Q7  
N
Q –1  
N
Q7  
No Chg. No Chg. No Chg.  
Z = High Impedance  
* At the positive clock edge, information in the 7th shift register stage is transferred to  
Q8 and Q .  
X = Don’t Care  
S
REV 3  
1/94  
Motorola, Inc. 1995  
123456

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