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MC10EP445MNR4G PDF预览

MC10EP445MNR4G

更新时间: 2024-11-02 19:30:51
品牌 Logo 应用领域
安森美 - ONSEMI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
19页 136K
描述
10E SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQCC32, LEAD FREE, LQFN-32

MC10EP445MNR4G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.4其他特性:ECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
计数方向:RIGHT系列:10E
JESD-30 代码:S-PQCC-N32JESD-609代码:e3
长度:5 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
湿度敏感等级:1位数:8
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):1.795 ns认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5 mm
最小 fmax:2800 MHzBase Number Matches:1

MC10EP445MNR4G 数据手册

 浏览型号MC10EP445MNR4G的Datasheet PDF文件第2页浏览型号MC10EP445MNR4G的Datasheet PDF文件第3页浏览型号MC10EP445MNR4G的Datasheet PDF文件第4页浏览型号MC10EP445MNR4G的Datasheet PDF文件第5页浏览型号MC10EP445MNR4G的Datasheet PDF文件第6页浏览型号MC10EP445MNR4G的Datasheet PDF文件第7页 
MC10EP445, MC100EP445  
3.3V/5VꢀECL 8-Bit  
Serial/Parallel Converter  
Description  
The MC10/100EP445 is an integrated 8–bit differential serial to  
parallel data converter with asynchronous data synchronization. The  
device has two modes of operation. CKSEL HIGH mode is designed  
to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode  
is designed to operate at twice the internal clock data rate of up to  
5.0 Gb/s. The conversion sequence was chosen to convert the first  
serial bit to Q0, the second bit to Q1, etc. Two selectable differential  
serial inputs, which are selected by SINSEL, provide this device with  
loop−back testing capability. The MC10/100EP445 has a SYNC pin  
which, when held high for at least two consecutive clock cycles, will  
swallow one bit of data shifting the start of the conversion data from  
http://onsemi.com  
MARKING  
DIAGRAM*  
MCxxx  
EP445  
AWLYYWWG  
LQFP−32  
FA SUFFIX  
CASE 873A  
D to D . Each additional shift requires an additional pulse to be  
n
n+1  
applied to the SYNC pin.  
Control pins are provided to reset and disable internal clock  
1
circuitry. Additionally, V pin is provided for single−ended input  
BB  
MCxx  
EP445  
condition.  
32  
1
The 100 Series contains temperature compensation.  
AWLYYWWG  
QFN32  
MN SUFFIX  
CASE 488AM  
G
Features  
1530 ps Propagation Delay  
5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode  
Differential Clock and Serial Inputs  
xxx  
A
WL  
YY  
WW  
= 10 or 100  
= Assembly Location  
= Wafer Lot  
V Output for Single-Ended Input Applications  
BB  
= Year  
= Work Week  
Asynchronous Data Synchronization (SYNC)  
Asynchronous Master Reset (RESET)  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
Open Input Default State  
CLK ENABLE Immune to Runt Pulse Generation  
These Devices are Pb−Free and are RoHS Compliant  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 17 of this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
June, 2014 − Rev. 16  
MC10EP445/D  

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