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MC10EP51DR2 PDF预览

MC10EP51DR2

更新时间: 2024-01-31 17:16:51
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
8页 79K
描述
3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

MC10EP51DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.37
其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V系列:10E
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:3000000000 Hz湿度敏感等级:1
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:-5.2 V
最大电源电流(ICC):47 mAProp。Delay @ Nom-Sup:0.42 ns
传播延迟(tpd):0.37 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mmBase Number Matches:1

MC10EP51DR2 数据手册

 浏览型号MC10EP51DR2的Datasheet PDF文件第2页浏览型号MC10EP51DR2的Datasheet PDF文件第3页浏览型号MC10EP51DR2的Datasheet PDF文件第4页浏览型号MC10EP51DR2的Datasheet PDF文件第5页浏览型号MC10EP51DR2的Datasheet PDF文件第6页浏览型号MC10EP51DR2的Datasheet PDF文件第7页 
MC10EP51, MC100EP51  
3.3V / 5VĄECL D Flip-Flop  
with Reset and Differential  
Clock  
The MC10/100EP51 is a differential clock D flip–flop with reset.  
The device is functionally equivalent to the EL51 and LVEL51  
devices.  
The reset input is an asynchronous, level triggered signal. Data  
enters the master portion of the flip–flop when the clock is LOW and is  
transferred to the slave, and thus the outputs, upon a positive transition  
of the clock. The differential clock inputs of the EP51 allow the device  
to be used as a negative edge triggered flip-flop.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
8
8
HEP51  
ALYW  
KEP51  
ALYW  
1
SO–8  
The differential input employs clamp circuitry to maintain stability  
under open input conditions. When left open, the CLK input will be  
D SUFFIX  
CASE 751  
1
1
pulled down to V and the CLK input will be biased at V /2.  
EE  
CC  
The 100 Series contains temperature compensation.  
8
1
8
1
8
350 ps Typical Propagation Delay  
Maximum Frequency > 3 GHz Typical  
1
HP51  
ALYW  
KP51  
ALYW  
TSSOP–8  
DT SUFFIX  
CASE 948R  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
L = Wafer Lot  
Y = Year  
H = MC10  
K = MC100  
with V = –3.0 V to –5.5 V  
EE  
Open Input Default State  
Safety Clamp on Inputs  
W = Work Week  
A = Assembly Location  
*For additional information, see Application Note  
AND8002/D  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10EP51D  
SO–8  
98 Units/Rail  
MC10EP51DR2  
MC100EP51D  
MC100EP51DR2  
MC10EP51DT  
SO–8  
SO–8  
2500 Tape & Reel  
98 Units/Rail  
SO–8  
2500 Tape & Reel  
100 Units/Rail  
TSSOP–8  
MC10EP51DTR2 TSSOP–8 2500 Tape & Reel  
MC100EP51DT TSSOP–8 100 Units/Rail  
MC100EP51DTR2 TSSOP–8 2500 Tape & Reel  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
April, 2001 – Rev. 3  
MC10EP51/D  

MC10EP51DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC10EP51DR2G ONSEMI

完全替代

3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock

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