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MC10EP52DG PDF预览

MC10EP52DG

更新时间: 2024-11-02 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
12页 163K
描述
3.3V / 5V ECL Differential Data and Clock D Flip−Flop

MC10EP52DG 技术参数

是否无铅:不含铅生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.09Is Samacsys:N
其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V系列:10E
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:4000000000 Hz湿度敏感等级:1
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):260电源:-5.2 V
最大电源电流(ICC):47 mAProp。Delay @ Nom-Sup:0.41 ns
传播延迟(tpd):0.38 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:3.9 mmBase Number Matches:1

MC10EP52DG 数据手册

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MC10EP52, MC100EP52  
3.3V / 5VꢀECL Differential  
Data and Clock D Flip−Flop  
Description  
The MC10EP/100EP52 is a differential data, differential clock D  
flipflop. The device is pin and functionally equivalent to the EL52  
device.  
http://onsemi.com  
Data enters the master portion of the flipflop when the clock is  
LOW and is transferred to the slave, and thus the outputs, upon a  
positive transition of the clock. The differential clock inputs of the  
EP52 allow the device to also be used as a negative edge triggered  
device.  
MARKING  
DIAGRAMS*  
8
1
8
8
HEP52  
ALYW  
KEP52  
ALYW  
G
The EP52 employs input clamping circuitry so that under open input  
1
conditions (pulled down to V ) the outputs of the device will remain  
EE  
G
SOIC8  
D SUFFIX  
CASE 751  
stable.  
1
The 100 Series contains temperature compensation.  
Features  
8
1
8
1
330 ps Typical Propagation Delay  
Maximum Frequency u 4 GHz Typical  
PECL Mode: V = 3.0 V to 5.5 V with V = 0 V  
8
1
HP52  
KP52  
ALYWG  
ALYWG  
TSSOP8  
DT SUFFIX  
CASE 948R  
CC  
EE  
G
G
NECL Mode: V = 0 V with V = 3.0 V to 5.5 V  
CC  
EE  
Open Input Default State  
Safety Clamp on Inputs  
Q Output Will Default LOW with Inputs Open or at V  
PbFree Packages are Available  
EE  
1
4
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
H
K
= MC10  
= MC100  
A
L
= Assembly Location  
= Wafer Lot  
5T = MC10  
3O = MC100  
Y
W
M
G
= Year  
= Work Week  
= Date Code  
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 6  
MC10EP52/D  

MC10EP52DG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP52DG ONSEMI

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3.3V / 5V ECL Differential Data and Clock D Flip−Flop
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