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MC10EP52D PDF预览

MC10EP52D

更新时间: 2024-11-01 22:30:59
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器触发器时钟
页数 文件大小 规格书
10页 86K
描述
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Data and Clock D Flip-Flop

MC10EP52D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:7.42
其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V系列:10E
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:4000000000 Hz位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):240
电源:-5.2 V最大电源电流(ICC):47 mA
Prop。Delay @ Nom-Sup:0.41 ns传播延迟(tpd):0.38 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn80Pb20)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.9 mm
Base Number Matches:1

MC10EP52D 数据手册

 浏览型号MC10EP52D的Datasheet PDF文件第2页浏览型号MC10EP52D的Datasheet PDF文件第3页浏览型号MC10EP52D的Datasheet PDF文件第4页浏览型号MC10EP52D的Datasheet PDF文件第5页浏览型号MC10EP52D的Datasheet PDF文件第6页浏览型号MC10EP52D的Datasheet PDF文件第7页 
MC10EP52, MC100EP52  
3.3V / 5VꢀECL Differential  
Data and Clock D Flip−Flop  
The MC10EP/100EP52 is a differential data, differential clock D  
flip−flop. The device is pin and functionally equivalent to the EL52  
device.  
Data enters the master portion of the flip−flop when the clock is  
LOW and is transferred to the slave, and thus the outputs, upon a  
positive transition of the clock. The differential clock inputs of the  
EP52 allow the device to also be used as a negative edge triggered  
device.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
8
The EP52 employs input clamping circuitry so that under open input  
8
HEP52  
ALYW  
KEP52  
ALYW  
conditions (pulled down to V ) the outputs of the device will remain  
1
EE  
stable.  
SO−8  
D SUFFIX  
CASE 751  
The 100 Series contains temperature compensation.  
1
1
330 ps Typical Propagation Delay  
8
1
8
1
Maximum Frequency u 4 GHz Typical  
PECL Mode: V = 3.0 V to 5.5 V with V = 0 V  
8
HP52  
ALYW  
KP52  
ALYW  
CC  
EE  
1
TSSOP−8  
DT SUFFIX  
CASE 948R  
NECL Mode: V = 0 V with V = −3.0 V to −5.5 V  
CC  
EE  
Open Input Default State  
Safety Clamp on Inputs  
Q Output Will Default LOW with Inputs Open or at V  
EE  
L = Wafer Lot  
Y = Year  
H = MC10  
K = MC100  
W = Work Week  
A = Assembly Location  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
June, 2004 − Rev. 3  
MC10EP52/D  

MC10EP52D 替代型号

型号 品牌 替代类型 描述 数据表
MC10EP52DG ONSEMI

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3.3V / 5V ECL Differential Data and Clock D Flip−Flop

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